Abstract: A microprocessor performs a fused multiply-accumulate operation of a form ±A*B±C using first and second execution units. An input operand analyzer circuit determines whether values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with partial products of A and B. The first instruction execution unit multiplies A and B and jointly accumulates C to partial products of A and B when the values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B. The second instruction execution unit separately accumulates C to the products of A and B when the values of A, B and/or C do not meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B.

Abstract: 2D nearest-neighbor quantum architectures for Shor's factoring algorithm may be accomplished using the form of three arithmetic building blocks: modular addition using Gossett's carry-save addition, modular multiplication using Montgomery's method, and non-modular multiplication using an original method. These arithmetic building blocks may assume that ancillae are cheap, that concurrent control may be available and scalable, and that execution time may be the bottleneck. Thus, the arithmetic building blocks may be optimized in favor of circuit width to provide improved depth existing nearest-neighbor implementations.

Abstract: For any multiplicative congruential generator (d, z) with an odd modulus d and a multiplier z coprime to d, a computationally innovative method is presented as specialized forms of 2nd degree spectral tests of (d, z^i) with 2?i?6, at the least. Providing with sharp and powerful sieving tools, the method enables the excavation of the integer set (d, z) as a generator of uniform and independent random numbers of excellent statistics with sufficiently long periods for simulations, and furnishes the selected generator with ways of clear, unambiguous and quantitative specifications of its performance.

Abstract: Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus.

Abstract: A method for processing a bitstream starts by shifting a bitstream of a first sample of a signal into a buffer. The buffer also holds bits of one or more additional bitstreams for one or more additional samples of the signal. Bits of a first half of the buffer are incrementally compared to corresponding bits of a second half of the buffer. Each bit of the first half of the buffer is compared to a corresponding bit of the second half of the buffer. A computation is performed on each bit of the first half of the buffer that is equal to a corresponding bit of the second half of the buffer. The results of the computations are summed to determine an output value for the first sample of the signal.

Abstract: A method for generating a signal for a transmission antenna in a magnetic resonance imaging system includes generating a real part and an imaginary part of a baseband signal, generating a real part and an imaginary part of variations in frequency and in phase, and performing a complex multiplication of the baseband signal with the variations in frequency and in phase and a radiofrequency carrier signal for modulation. The method also includes modifying the modulated signal, and may include establishing a characteristic angle for a phase shift of the modified signal, and correcting the modulation based on the established angle in a closed-loop control.

Abstract: A processor includes a hash register and a hash generating circuit. The hash generating circuit includes a novel programmable nonlinearizing function circuit as well as a modulo-2 multiplier, a first modulo-2 summer, a modulor-2 divider, and a second modulo-2 summer. The nonlinearizing function circuit receives a hash value from the hash register and performs a programmable nonlinearizing function, thereby generating a modified version of the hash value. In one example, the nonlinearizing function circuit includes a plurality of separately enableable S-box circuits. The multiplier multiplies the input data by a programmable multiplier value, thereby generating a product value. The first summer sums a first portion of the product value with the modified hash value. The divider divides the resulting sum by a fixed divisor value, thereby generating a remainder value. The second summer sums the remainder value and the second portion of the input data, thereby generating a hash result.

Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (“FIR”) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.

Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.

Abstract: A data processing apparatus has a processing circuitry for performing a floating-point square root operation on a radicand value R to generate a result value. The processing circuitry has first square root processing circuitry for processing radicand values R which are not an exact power of two and second square root processing circuitry for processing radicand values which are an exact power of 2. Power-of-two detection circuitry detects whether the radicand value is an exact power of two and selects the output of the first or second square root processing circuitry as appropriate. This allows the result to be generated in fewer processing cycles when the radicand is a power of 2.

Abstract: A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N-bit portion of the group. The partial products are added while represented in the redundant representation.

Abstract: A non-transitory storage device containing software than, when executed by a processor, causes the processor to generate a projection set of polynomials based on a projection of a space linear combination of candidate polynomials of degree d on polynomials of degree less than d that do not evaluate to less than a threshold on a set of points. The software also causes the processor to compute the singular value decomposition of a matrix containing the difference between candidate polynomials evaluated on the points and the projection set of polynomials evaluated on the points, and to partition the polynomials resulting from the singular value decomposition based on a threshold.

Abstract: An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: A data processing apparatus includes a computing unit that performs a matrix computation between data streams whose unit data is of a matrix format; a determining unit that for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value; a converting unit that converts the value of each element into a significand value of the element, according to the exponent value determined by the determining unit; and an output unit that correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit.

Abstract: A high performance, low complexity phase shift network may be created with one or more non-first-order all-pass recursive filters that are built on top of a plurality of first-order and/or second-order all-pass recursive filters and/or delay lines. A target time delay, whether large or small, may be specified as a constraint for a non-first-order all-pass recursive filter. A target phase response may be determined for the non-first-order all-pass recursive filter. Phase errors between the target phase response and a calculated phase response with filter coefficients of the non-first-order all-pass recursive filter may be minimized to yield a set of optimized values for the filter coefficients of the non-first-order all-pass recursive filter.

Abstract: A solution method for solving an underdetermined system of linear equations, in which the number of elements of a variable to be determined is N and the number of linear equations is M (where M and N are integers satisfying 1?M<N), using iterative calculations, comprises, in each iteration: an extraction step of extracting at least M non-zero element candidates from the N elements of the variable; a subproblem solving step of setting a subproblem having only the extracted non-zero element candidates as a variable, and solving the subproblem as an ill-posed problem; and an updating step of updating values of the N elements of the variable to be determined on the basis of values of the non-zero element candidates obtained in the subproblem solving step.

Abstract: According to one embodiment, a permutation generator is described comprising a memory configured to store, for each number of a predetermined set of numbers, whether the number has already been included in a number sequence; a receiver configured to receive a random number; a determiner configured to select a number from those numbers of the set of numbers that have not yet been included in the number sequence as next element of the number sequence based on the random number and an output configured to output the selected number as the next element of the number sequence.

Abstract: A method, system, and processor-readable storage medium are directed towards calculating approximate order statistics on a collection of real numbers. In one embodiment, the collection of real numbers is processed to create a digest comprising hierarchy of buckets. Each bucket is assigned a real number N having P digits of precision and ordinality O. The hierarchy is defined by grouping buckets into levels, where each level contains all buckets of a given ordinality. Each individual bucket in the hierarchy defines a range of numbers—all numbers that, after being truncated to that bucket's P digits of precision, are equal to that bucket's N. Each bucket additionally maintains a count of how many numbers have fallen within that bucket's range. Approximate order statistics may then be calculated by traversing the hierarchy and performing an operation on some or all of the ranges and counts associated with each bucket.

Abstract: There is provided a matrix calculation apparatus. The apparatus includes: a matrix calculation formula display controller configured to display a matrix calculation formula on a display unit, wherein the matrix calculation formula comprises a first matrix; a matrix display controller configured to display a second matrix on the display unit; a submatrix receiver configured to input the second matrix into a certain element of the first matrix as a submatrix of the first matrix in response to a user operation; and a matrix size change display controller configured to change a size of the first matrix in accordance with a size of the second matrix and the certain element of the first matrix into which the second matrix is input and then display the matrix calculation formula.