Abstract: Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the particular highest priority requesting internal or external interrupt. All further interrupts are suppressed during the time required to service the interrupt and, depending upon the type of interrupt, either the internal or external interrupt may be suppressed for one or two instruction times for debug purposes or under computer program control as required for a particular operation.

Abstract: A data processing system which employs a CPU and a MOS memory, the memory requiring replenishing or refreshing periodically. The CPU includes microcode containing microinstructions, the microinstructions providing control for the CPU including control for the memory. The refreshing scheme employs apparatus for decoding of these microinstructions and for providing refreshing signals to the memory in such a manner that all non-refreshing operations of the data processing system proceed without being delayed by operation of the refreshing apparatus. The algorithm which guides the operation of the CPU includes a number of system operating modes (such as FETCH, MULTIPLY, DIVIDE, HALT, DATA CHANNEL, and others). These modes each contain an operating state designated RAC.fwdarw.MEM which indicates that a refresh signal automatically is forwarded to the MOS memory when a particular operating mode runs through its respective operating states.

Abstract: A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.

Abstract: A multiprocessor microcomputer system having two or more substantially independent processors each of which has its own bus-type interconnection structure, and a shared memory accessible by any of the processors without interferring with the proper operation of the other processors. Controlled access to the memory by connecting the memory to the processor requesting access when only one such request is present and to the last processor to have received access when more than one request is received simultaneously allows autosynchronous operation, automatic selection of priority and high speed of operation.

Abstract: A computer which is configured to perform its operations in overlapped fashion. During each computer cycle the next instruction is fetched, the function designated by the previous instruction is executed, and values are stored that were computed with respect to the instruction previous to the one being executed. Thus a three-way overlap is effected. To minimize time penalties due to conditional branches and jumps, each instruction word includes two next instruction address fields, two function fields and two deferred action fields. The computer includes decision logic for providing binary decision signals for conditionally selecting one of the fields from each of the next address fields, the function fields and the deferred action fields thereby conditionally fetching the next instruction, conditionally selecting the function to be performed and conditionally storing values during the same cycle in accordance with the decision signals.

Abstract: An interface which connects input/output (I/O) controllers to a data channel in a data processing system. A bidirectional priority bus is provided interconnecting the channel with the controllers. Each controller is assigned a priority level. When a controller requires service, it signals the channel over a common request line and the channel responds with a channel select signal. Each requesting controller gates a binary number corresponding to its priority level onto the common priority bus. Contending controllers resolve priority among themselves by monitoring the priority bus. If a controller detects a higher priority level than its own level on the bus it removes its priority number from the bus. The highest priority controller then activates an acknowledge signal and places its device address on a bidirectional data bus in response to a ready signal from the channel.

Abstract: An automatic clock phase adjustment circuit is incorporated in a local unit of a data clocking system. The local unit also includes a clock pulse generator and a local data storage device. The system also includes a remote unit having a remote data storage device. The automatic clock phase adjustment circuit receives clock pulses from the generator and produces output clock pulses having first and second half periods interconnected by a clocking transition which when applied to the remote storage device causes clocking out of data to the local storage device. The circuit also produces a sampling pulse during each of the first and second half periods of the output clock pulses and is operable to detect in which particular one of the half periods a positive transition in the incoming data has occurred during the interval of a sampling pulse in that half period.

Abstract: In a system for producing a display in an x,y coordinate system which system produces only a single display point for each display position on the x-axis, a circuit for producing rise lines and fall lines parallel to the y-axis to connect the display points in adjacent positions on the x-axis. The circuit includes a shift register for storing a line of data, a shift register for storing rise line positions, a shift register for storing fall line positions, and AND gates for terminating rise lines and fall lines upon reaching a display in an adjacent position on the x-axis.

Abstract: A data processing system includes means which are operative when the system is conditioned for operating in a trace mode during the processing of program instructions, to record the op code of each instruction designated as executable by the bit contents of a table referenced before beginning instruction execution. When the op code of an instruction is designated by the table as not being executable, the system traps the instruction and generates a call to the operating system software without recording its op code. The selective recording and trapping of instruction operation codes facilitates diagnosis of program errors or faults within the system. This is particularly valuable when the system includes emulation apparatus which may not be completely compatible in every detail with the system being emulated.

Abstract: Apparatus for processing data whereby a digital control signal is generated for effecting the presentation of a selected portion of a map image on a raster display. The data includes stored data words describing characteristics of line segments utilizable to construct the image. The line segments include line vectors representative of elongated features of the image and boundary vectors identifying boundaries between image areas of different brightness. Processing of the data is accomplished by means of two control loops. The first control loop performs selected macrosteps including arithmetic manipulations, on the data words to effect generation of the digital control signal. The second control loop effects selection of the macrosteps to be performed by the first loop and routes the data words within the generator in response to the instant data being processed by the generator.

Abstract: A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes.

Abstract: A microprocessor with a two bus structure and modulo addressing hardware which converts any section of main memory into an apparent circular address space for use as a five-fold data register. The modulo addressing hardware has a capability for circularly loading data into a sequential order or accessing data repeatedly for the evaluation of recursive algorithms. Thus, the modulo addressing hardware is useful in the rapid processing of such recursive software algorithms and in the solution of various mathematical series. More generally, it is useful for the rapid access of any data in memory. The described microprocessor uses the modulo addressing hardware concurrently with the execution of data manipulation instructions. A 64 bit wide instruction allows control of both modulo addressing hardware and the microprocessor CPU in a single micro instruction.

Abstract: A method and apparatus for accessing data blocks in a computer system having multiple-disk drive rotational position sensing which is not centrally synchronized and where data read and write requests are normally weighted by the order of availability of requested data blocks. The weighting of the priority, or queue position, of selected data blocks is modified by advancing the apparent initial location of data blocks designated for preferental access and maintaining an availability signal, or peripheral interrupt, for an extended period. A special pre-data-transfer instruction indicates the duration of the peripheral interrupt. A circuit for implementing the invention has a storage register for receiving the special instruction, a down counter for decrementing for the duration of the designated pre-data-interrupt and an interrupt duration control latch for issuing and extinguishing the interrupt.

Abstract: A microprogrammable CPU for a computer utilizes an architecture wherein macro instructions of the computer repertoire are executed by micro instruction routines stored in a control store memory. The micro instruction routines are comprised of micro instruction words for controlling the micro operations to be performed in executing the macro instructions. The CPU includes a plurality of local processors each configured to perform a plurality of the micro operations. A macro instruction fetched into the macro instruction register of the computer addresses the corresponding micro instruction routine in the control store memory and the plurality of local processors operate concurrently to simultaneously perform the micro instructions of the routine on behalf of the fetched macro instruction. Thus a stream of macro instructions flowing through the macro instruction register is decomposed into a plurality of concurrently executed micro instruction streams flowing through the respective local processors.

Abstract: A first in-first out buffer memory coupled to a system bus receives all information transferred over the bus. Logic associated with the buffer memory tests if the information received is intended to update main memory or is in response to a cache request. The information is written into cache if the main memory address location is stored in a cache directory. The information received in response to a cache request is stored in a cache data buffer. Other information is discarded.

Abstract: A data processing system includes a central processor subsystem, a main memory subsystem and a cache subsystem, all coupled in common to a system bus. During the overall system initialization process, apparatus in the cache subsystem effects the transfer of information from the main memory subsystem to the cache subsystem to load all address locations of the cache subsystem. The transfer of information from the main memory subsystem to the cache subsystem starts from the lowest order address locations in main memory and continues from successive address locations until the cache subsystem is fully loaded. This assures that the cache subsystem contains valid information during normal data processing.

Abstract: During system initialization, a cache is completely loaded with valid information from main memory. The directory and data buffer are organized in levels of memory locations. Each level of the directory and data buffer is loaded in turn from main memory. Round Robin apparatus, which is preset during system initialization, identifies the next level into which a replacement data word is written on a first in-first out basis. The round robin count for each address location of cache indentifying the next level to be written is stored in a random access memory (RAM). The contents of a particular address location of RAM is incremented each time replacement information is written into that address location in cache.

Abstract: A data processing system for reading or writing data comprises a data memory unit and a processing unit, the data to be read from or written to the data memory unit is being serially transferred bit by bit over a single line connected between the data memory unit and the processing unit. The processing unit is operated in accordance with an instruction specified by instruction addressing information which is produced by an instruction counter. The data is specified by data addressing information which is produced by a means for specifying the address of the data memory unit. Both the lower bits of the data addressing information and the lower bits of the instruction addressing information are jointly produced by the lower bit stages of the instruction counter. The upper bits of the data addressing information are momentarily stored in an upper bits specifying register during one read or write operation while one execution of one data bit data is performed.

Abstract: A data display communication system wherein data generated locally by a keyboard or generated remotely and communicated by modems is displayed on a display device. Data displayed on the screen can be edited or reformatted prior to storage, print-out, or transmission to a remote location. Data communicated between storage and the central processing unit is handled in blocks that make up one full line of characters on the display device. All edit and format functions are performed on the basis of these blocks of data. Timing for the display device controls the operation of the system. The communication system utilizes a microprocessor operating in conjunction with specific hardware logic to handle display oriented operations.

Abstract: A racing circuit wherein request signals which are asynchronously and simultaneously generated by a plurality of processor units for requesting the use of a common resource such as a memory are temporarily stored, and one of the stored request signals is selected so that the corresponding processor unit may access and use the common resource. The circuit provides a buffer arrangement for causing a first received request signal to lock out other request signals which follow the first signal too closely, and for providing access to the common memory or other device in the order in which access requests were received. The processor unit may control the racing circuit so that the processor unit may attain the exclusive use of the common resource as long as it desires.