Abstract: A terminal is connected by a transmission link to a computer coupler. The rminal has a reader for a worker's card or badge. A number written on the badge is sent to the computer for verification and is echoed back if OK. The return number is checked against the number sent and if still OK the badge number is displayed. Communication takes place over two telephone lines which may be taken from amongst pre-existing telephone lines in a work location. Other data such as time and total hours worked may be displayed by the terminal once a badge has been verified.

Abstract: Apparatus for providing, in a multiplexed fashion, both the operations of framing to determine the position of a framing bit in a stream of data bits and, after framing has occurred, the job of providing slip control for an elastic store. Since these are essentially exclusive functions in that framing only need occur at the initial portion of a cycle and slip control need only occur after framing has been successfully completed, there is no interference between the two functions. The framing is obtained by supplying input data bits to a memory for intermediate storage and then an integral number of frames later comparing the presently received data with that received previously, and if a negative comparison occurs, eliminating that particular bit as a candidate for the framing bit. The same memory is then used along with the same addressing means for providing an elastic store along with slip control.

Abstract: A solid state unit is provided which is intended as an aid in the maintenance and upkeep of a motor vehicle, and which serves as a reminder of the next maintenance mileage point, and the items to be serviced at the next maintenance operation. The unit also serves as a permanent record of the scheduled maintenance that has been performed on the vehicle throughout its lifetime. The unit is intended to be mounted under the dashboard, or at any other convenient location within the vehicle. The unit includes a programmable read-only memory (PROM) in which data is permanently stored representing the mileage at which the next maintenance operations are to be performed, as well as data identifying the items requiring servicing at the next maintenance point.

Abstract: An input/output controller provides a numer of adjustable timers for timing events such as for polling external devices and includes circuitry which generates interrupt vector signals upon the occurrence of certain events, including the expiration of time set in the adjustable timers and also upon receipt of signals from the external devices. The interrupt signals may be selectively masked when it is not desirable or practical for an interrupt to occur. The controller is an MOS N-channel device on a single chip and is packaged in a 40 pin package and is compatible with a Model TMS 8080 Microprocessor Unit.

Abstract: In a microprogrammed pipelined data processing system, a template family interfacing structure sequences a plurality of templates to the pipelined system for control thereof, each template therein comprising a set of microinstructions for controlling each stage in the pipelined system. The templates are stored in a template micromemory system addressed by an address register and read to a control register. Parameters, grouped into template "Families", of the next template to be used and family parameters of the current template in use are utilized in conjunction to control the initiation of the next template to avoid conflict in any stage in the pipelined system.

Abstract: A microprogrammed digital computer employing a plurality of programmable read only memories containing stored control words which are specially chosen so as to provide for microinstruction sequencing in a manner which in the first instance assumes that no branching possibilities are present, even though one or more branching possibilities may in fact be present in the microinstruction flow path. The correctness of microinstruction sequencing is monitored concurrently with the execution of a microinstruction during each cycle for which a branching decision is required. When an incorrect assumed sequence is detected, correction is provided using microinstruction indexing and inhibiting signals which are selectively provided in response to the states of selected system conditions during the cycle.

Abstract: An on-line computerized system useful in automatic document control and inventory systems such as that needed in libraries with a large number of books, records, films, and other items. In the library system disclosed, each borrower and each item within the library is given a unique identification number. The system includes automated Check-In/Check-Out terminals at each branch library which are interfaced to a computer for facilitating patron services and permitting fast, on-line storage and retrieval of data concerning overdue fines, reserve books, expired and delinquent patron cards, and other pertinent information.

Abstract: An electronic data processing system which utilizes a variable timing period that is varied in accordance with the access time of the digital devices or circuits utilized in each step of the data processing program. In one embodiment, the data processing system is a computer which performs the basic arithmetic and logical operations. The computer utilizes three memories which have different access times. One memory stores instruction words specifying steps in a computer program for performing basic arithmetic and logical operations involving predetermined data words; another memory stores the data words; and, the third memory stores control words specifying the various machine operations required to execute the corresponding instruction. The three memories can be read out simultaneously, two at a time, or one at a time. In each case, the timing strobe which initiates the next step in the program is generated immediately after the slowest memory utilized in that step is ready for the next readout.

Abstract: An MOS digital computer incorporated on a single chip (monolithic structure) which includes a central processing unit (CPU), random-access memory (RAM), and a programmable read-only memory (PROM). A program counter is used to fetch instructions stored in the erasable PROM, and may also be used to fetch instructions from an external memory. The PROM may also be externally addressed for testing, or may be electrically isolated from the remainder of the computer to permit execution of external instructions for testing the CPU and RAM.

Abstract: A digital processor programmed to perform multi-tasks which includes a hardware dispatcher for selecting tasks. The dispatcher receives a plurality of dispatcher requests and determines the highest priority request. The dispatcher then selects the appropriate program routine. Each routine is divided into segments, and the status of the routines are stored in registers. When a routine is selected, the appropriate segment in the routine is also selected. At the end of each segment the dispatcher requests are re-examined.

Abstract: An interface circuit for use in a data transmission system has a first port for connection to a 16 wire data highway of the type proposed by the I.E.C. (International Electrochemical Commission) for the interconnection of instruments, and a second port capable of being connected to an eight-wire or two-wire data link. The interface circuit includes an encoding circuit operative to encode at least some commands applied to the first port, and an enabling circuit for selectively enabling data applied to the data terminals of the first port and the encoded commands to pass to the second port.

Abstract: Distributed control architecture for a multiprocessor system includes a control processor operating on system programming instructions for executing system supervisory and task management functions, and a control bus over which it outputs execute instruction words containing a pointer address. Program storage stores threaded link lists of intermediate level instruction words, each list head being pointed to by the pointer address of respective execute instruction words. A first subunit processor for executing a first type function has a control input connected to a first distributed control interface processor and includes first post and wait logic for posting a signal indicating completion of a first type function.

Abstract: An address conversion device for use with computer systems including a central processing unit and peripheral memory storage devices, such as discs, tapes and bubble memories, which serve for secondary data storage and in which binary data elements are stored in sequential addressable storage sectors. Such storage sectors have precise physical locations on the peripheral storage units. The address conversion device includes a first conversion unit which controls the conversion of user program addresses to logical addresses reflecting the logical structure of the data files stored in the peripheral storage units and a second conversion unit which converts the logical addresses to precise physical addresses of sectors of the secondary storage units in the form of electrical signals, such that the secondary storage units can be addressed as if they were random access units.

Abstract: A parallel processor having a large number of elementary processors connected in parallel to an address bus and a control bus. Each elementary processor contains a memory and control and processing circuits to perform calculations on bits addressed in the memory and bits coming either from this memory or from a peripheral unit. Each elementary processor further contains a small capacity fast memory and the control and processing circuit contains a single storage flip-flop able to perform calculations in series on the bits extracted from the memories and/or coming from the peripheral unit. All the fast memories are parallel connected.

Abstract: A data rate control device interfacing between a computer and a communication line facilitates reading out of data from the computer at a fast rate and then transmitting that data at a slow rate on the communication line with allowance being made between data transmissions for reflections and echoes on the line to die down. The control device includes a clock generator, control logic and a clock transmitter for sending out Fast Clocks and causing the serial reading in of data to a shift register of the control device. Once the presence of one character of data is detected in the register by the control logic, the Fast Clocks are terminated and Slow Clocks are sent to the register for serial reading out of the data character to a loop transmitter of the control device for transmission of the data character on the communication line.

Abstract: A digital wave synthesizer provides one of a plurality of available analog output signals in response to and corresponding to a digital input signal. Each of the available plurality of analog output signals is made up of n successive segments of periods A and B. Segment information is stored in a logic array in such a manner that the segment number and the desired frequency output provides any of the n segments of any of the plurality of analog output signals with the appropriate A or B period. The successive order of segments is not altered by a change in the digital input signal requiring a change in the output signal frequency. An increase in frequency simply requires that a succeeding segment have a shorter A or B period and that a lower frequency have a longer A or B period. The voltage provided in a voltage distribution network is always the same for a particular number of segments irrespective of the output frequency required. Therefore, when a frequency change is required, there is no voltage shift.

Abstract: A data processing system having a principal apparatus, such as a programmable large-scale data processing system, and a secondary apparatus. The secondary apparatus performs fault detection and analysis on the principal apparatus. The secondary apparatus under control of a secondary program and independently from the principal apparatus, accesses information from different points, such as latch circuits, throughout the principal appartus. The accessed information is utilized by the secondary apparatus to form an actual checksum having a value determined by the accessed information. The actual checksum thus formed is compared with an expected checksum provided from storage by the secondary apparatus. If the actual and expected checksums are different, a fault condition is indicated. An analysis of selected subsets of points in the primary apparatus is made using a compacted scan composed of the values of the selected subset of points.

Abstract: In a network for transferring a source field in a source word into a destination field in a destination word two basic hardware sub-functions are utilized: rotation and mask vector generation. In the network the destination field of a destination word is masked. Concurrently in the network, a source word is rotated bringing the source field thereof into corresponding alignment with the masked destination field and all but the source field of the source word is masked. Subsequent logical combining of the masked destination word and the rotated and masked source word generates the desired field transference. In one embodiment the required masking operation is accomplished during a single pass of the destination and source words through the network. In an alternate embodiment using less masking hardware only half of the required masking is accomplished during each pass and two passes are required before the logical combining to achieve the desired field transference.

Abstract: A computer terminal for providing a visual display of linguistic characters in response to character data information from an external computer. The computer display terminal can be semipermanently configured in response to externally supplied configuration information. The terminal includes a microprocessor unit formed by a microprocessor, a ROM for instruction codes and a RAM for temporary data storage. A data communications channel interfaces with the microprocessor unit, receives the character information from the external computer, and provides such information to the microprocessing unit for storage in its RAM. A CRT or other display interfaces with the microprocessor unit and visually displays character information stored in the RAM. A keyboard or other input interfaces with the microprocessor unit and provides a means for inputting externally supplied terminal configuration information.

Abstract: A minimum number of clock pulses required for keeping an electronic component in a waiting condition or state are intermittently applied to the electronic component, thereby minimizing the heat dissipation thereof. A control circuit, utilized in the invention, provides an output signal which permits continuous clock signals to be applied, for example, to memory chips, during read and write periods, but such control circuit reduces the number of clock signals applied to the memory chips during periods when the read and write processes are not required.