Abstract: A data processing system includes central storage where access to data is by central storage addresses. Instructions normally include a logical or virtual address which is translated to a real central storage address using dynamic address translation (DAT) with or without an access register (AR) translation mechanism. When in AR mode, and with DAT on, addressing of instructions or data in central storage can be effected by specifying real central storage addresses and eliminate the DAT and AR translating process.

Abstract: A method, and circuitry that operates in accordance with the method, for generating an entry for a translation buffer in a data processor that employs virtual memory addressing. The method includes the first steps of storing a Faulted Virtual Address in a first register (96) and a Zone Table Address (ZTA) in a second register (94). In response to the execution of a micro-instruction, a next step forms an address in memory of a Zone Table Entry (ZTE) by selectively combining a first portion of the content of the first register with the content of the second register, while simultaneously testing the ZTA for physical address mapping. In response to an execution of a next micro-instruction, a next step accesses the ZTE with the formed address, and forms an address in memory of a Segment Table Entry (STE) by selectively combining a second portion the content of the first register with a content of the ZTE, while simultaneously testing the ZTE for a Zone fault.

Abstract: A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page is unknown. There are L different possible page sizes where L is a positive integer greater than one. Each of the L different page sizes is selected to be a test page size and a test is performed. During the test, a pointer into a translation storage buffer is calculated. The pointer is calculated from the virtual address to be translated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The pointer points to a candidate translation table entry of the translation storage buffer. The candidate translation table entry has a candidate tag and candidate data.

Abstract: A cache memory unit for use in a multiprocessor. The unit includes a data memory, a tag memory, a valid flag section, and an address bus, a comparator, and a clear signal producing section which produces a monitoring clear signal based on an output from the comparator and a monitoring strobe signal. The valid flag section receives the monitoring clear signal from the clear signal producing section. The cache memory unit further includes a monitoring strobe signal activating section which causes the monitoring strobe signal to be inputted to the clear signal producing section active or inactive whereby the valid flag section is cleared or prohibited from being cleared. The monitoring strobe signal activating section is reset when the operation enters into an in-circuit emulator (ICE) program and is set when the operation is freed from the ICE program. The cache memory unit enables the system to be debugged precisely without no delay in the execution of time.

Abstract: The signal processor including a CPU 10 which selects a context register 16, the contents of which configure an address generator 20 and a data type converter 22. A narrow parameter from the CPU 10 produces a broad address for the generator 20 to pass to the memory 28. The converter 22 converts data between memory 28 format and CPU 10 format. A different context register 16 may be selected by each code line of software. The generator 20 preferably calculates a data element length which is the product of an odd number and a power of two, each number being specified in the content of the Context Register 16. Elements are clustered into groups, one group for each element length, and the groups are arranged in order of ascending element length. The index identifying the individual element of a group with a larger element length does not begin with zero (or one).

Abstract: A method for implementation of muti-port interleaved memory systems comprising any prime number P of memory modules each of which contains a power of two memory banks. Each memory bank comprises a power of two memory locations. In this method, sequential addresses are mapped into sequential memory modules, and the addresses mapped into a given module are mapped into distinct memory locations within the module without explicit and implicit operations of division by the prime number P. The method embodies families of functions any one of which can be used for the bijective mapping of addresses into memory locations within a memory module. Furthermore, any of the functions is computable in O(1) gate delays employing O(log.sub.2 P) logic gates. A multi-port interleaved memory system with P memory modules can serve multiple requests for vectors of data, where each memory port is used to serve a request for a vector of data.

Abstract: As a TLB (translation look-aside buffer) of a fully associative system is organized, a first CAM (content addressable memory) cell array and a first RAM (random access memory) cell array which together make up one entry are arranged in such a way that they face each other across a control circuit. As a cache memory of a fully associative system is organized, a second CAM cell array and a second RAM cell array which together make up one entry are arranged in such a way that they face each other across the control circuit. Additionally, the second CAM cell array is located next to the first RAM cell array, whereas the second RAM cell array is located next to the first CAM cell array. These four cell arrays make up one section. At the time of a hit in the first CAM cell array, the control circuit enables readout of the first RAM cell array, while it, at the time of a hit of the second CAM cell array, enables readout of the second RAM cell array.

Abstract: A resource access security system for use in a data processing system for controlling access to resources correspondingly assigned to addresses in an address space of the data processing system by the use of descriptors. The descriptors correspondingly identify the resources and access to the resources is controlled by requiring the input of a descriptor of the resource to which access is sought. The resource access security system controls access to the resources by translating each descriptor being taught to gain access to a resource by use of a plurality of tables having stored therein user/job information, domain information and page information and a descriptor translator which controls the descriptor translation process. The descriptors are virtual addresses of addresses assigned to the resources of the data processing system.

Abstract: A microprocessor has a CPU, an address converter which converts a logical address to a physical address, first and second latches which are controlled by a control signal and store the physical addresses, and a dual port cache memory device. The dual port cache memory device has decoders which operate according to second parts of outputs of the latches, dual port memory arrays which can be independently accessed by outputs of the decoders, a comparator which compares a physical address output from the dual port memory array and a first part of an output of the first latch to determine if they are the same, and a second comparator which compares a physical address output from the dual port memory array and a first part of an output of the second latch to determine if they are the same.

Abstract: A one-chip address generator for producing a sequence of address signals for application to a memory containing a plurality of circular buffers. The address generator chip is capable of processing service requests from a plurality of channels on a prioritized basis. Service requests can arrive asynchronously at different rates. A channel-specific length or overlap value can be assigned to each servicing of a request. A seamless pipeline structure is provided for processing the service requests of subsequent channels immediately after completion of service for a first requesting channel.

Abstract: A sequential access memory employs a dynamic type row address pointer 2 as a row address pointer for selecting row selection lines of a memory cell array 1, and a static type column address pointer 3 as a column address pointer for selecting a column selection lines 5 of memory cell array 1.

Abstract: Each of a plurality of pages of video data are shuffled, each of the pages being composed of a plurality of blocks of data, using a data memory having a memory capacity of one page. The one page data memory temporarily stores data in a current page. A data address generator generates an address of the data memory so that the data in the current page are written into the data memory in a first sequence and the written data are read out from the data memory in a second sequence which is different from the first sequence to thereby shuffle the data in the current page. The data address generator generates the address such that data in a block in the current page is read from a portion of the data memory indicated by the address generated by the data address generator, and such that data in a block in a next page is written into the portion of the data memory indicated by the address generated by the data address generator.

Abstract: A high performance computer pipeline allows reading or writing of data during a single clock cycle. A write queue is provided for temporary buffering of data to be written back to memory. Data is transferred from the write queue to memory during otherwise unused memory access cycles.

Abstract: A physical space management table is disposed outside the microprocessor in order to hold attribute data of the regions of the physical space held as a set of a plurality of regions in a manner corresponding to the regions of the physical space. The microprocessor is provided with a physical space management unit which fetches the attribute data from the physical space management table and manages them. The physical space management unit includes a physical space management table search control circuit, and a physical data buffer which primarily holds the attribute data obtained by the physical space management table search control circuit and the physical address in a manner corresponded to each other.

Abstract: A caching arrangement which can work efficiently in a superscaler and multiprocessing environment includes separate caches for instructions and data and a single translation lookaside buffer (TLB) shared by them. During each clock cycle, retrievals from both the instruction cache and data cache may be performed, one on the rising edge of the clock cycle and one on the falling edge. The TLB is capable of translating two addresses per clock cycle. Because the TLB is faster than accessing the tag arrays which in turn are faster than addressing the cache data arrays, virtual addresses may be concurrently supplied to all three components and the retrieval made in one phase of a clock cycle. When an instruction retrieval is being performed, snooping for snoop broadcasts may be performed for the data cache and vice versa. Thus, for every clock cycle, an instruction and data cache retrieval may be performed as well as snooping.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: A compact, low power consumption, light weight, highly reliable and high speed information processing system is provided by employing a semiconductor auxiliary storage device in lieu of conventional magnetic storage or memory elements, such as floppy or hard disks. An access request to such a magnetic storage or memory element is converted to an access request for the semiconductor auxiliary storage which uses semiconductor integrated circuits without requiring any modification of existing programs, such as, application software and disk operating systems. A memory circuit in the semiconductor auxiliary storage comprises ROM and RAM, and a portion of the ROM contents is copied into the RAM so that access modification for programs and data is permitted while the basic program and data is retained in a nonvolatile manner.

Abstract: An absolute address translated from a logical address input by a user program by an address translation circuit and a prefix translation circuit, is compared with contents of a virtual processor prefix register. On the basis of the comparison result, a multi-processor field of a translation lookaside buffer (TLB) has a value indicating whether or not the entry corresponds to an area common among virtual processors. The MP field of the TLB is compared with contents of the multi-processor register, and a virtual processor field of the TLB is compared with contents of a virtual processor register. If the value coincides with the multi-processor field or if the value does not coincide with the multi-processor field and the value coincides with the virtual processor field, contents of an absolute address field of the TLB are input to an absolute address register. This increases the effective capacity and utilization of the TLB to avoid decreasing of performance of the virtual machines.

Abstract: A cache memory device including first and second address selectors and a control device for controlling the selection of two addresses out of four types of addresses. The four address types are instructions addresses successively generated by an increment of a program counter, a branch address for instruction fetch in a branch target based on a conditional branch instruction or the like, a data address for data access based on load instruction or store instruction, and a physical address for regulating data consistency between the cache memory device and other memory devices. A first memory array for storing tag addresses and a second memory array for storing instructions and data have two ports to access two selected addresses received from the first and second address selectors independently. Accordingly, access penalties by an RISC microprocessor are reduced in a processor unit in a multiprocessor system.

Abstract: The data processor accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under the user mode being able to