Abstract: A 1-dimensional history table, which has been named a TLBLAT, is used to predict some or all of the real address bits that correspond to (i.e., translate from) any given virtual page address in order to provisionally access a real address based cache. The selection of a TLBLAT entry from given virtual address is based on certain address bits in the virtual address. The selection of a TLBLAT entry may also be based on the hashing of such virtual address bits together with other information in order to achieve sufficient randomization. At the minimum, each TLBLAT history table entry records the bits (one or more) necessary for prediction of the congruence class in a real address based cache. The set-associativity of the cache may be as low as one (i.e., a direct-mapped cache).

Abstract: In a register file having an overlap-window arrangement in which 64 registers are divided into eight windows W0 to W7 each containing 16 registers R0 to R15, memory cells are divided into two memory cell arrays, i.e., a first memory cell array containing registers R0 to R7 of odd-numbered windows (or registers R8 to R15 of even-numbered windows), and a second memory cell array containing registers R0 to R7 of even-numbered windows (or registers R8 to R15 of odd-numbered windows). Each of the registers has one read word line. According to the exclusive logical sum of the least significant bit of a window No. signal and the most significant bit of a register address signal, an output selection circuit selects one of two data simultaneously read from the two memory cell arrays. There is thus provided a register file which is small in circuit scale and assures high-speed reading.

Abstract: A method for assembling swap blocks of virtual pages for transfer between a backing store and physical memory in a data processing system. The method includes segregating all virtual pages resident in physical memory between an active list and an inactive list. Virtual pages are then assigned to the inactive list by groups where each page in a group belongs to a single owning task or object. From a group, virtual pages are assigned to a swap block based upon correlation of most recent use. The swap block may then be paged out in a single operation to a backing store. A list of the group members is kept to permit page in to physical memory upon reference to a member of the swap block.

Abstract: A level-2 virtual machine is constructed under the control of a level-1 operating system (OS) operating on a real machine (level-1), and a level-3 virtual machine is constructed under the control of another operating system (OS) operating on the level-2 virtual machine. A level-3 virtual address generated in the level-3 virtual machine is translated to a level-2 virtual address, which is further translated to a level-1 virtual address. A third predetermined main storage address is added to the level-1 virtual address to generate a level-1 absolute address. The translated address is checked as to whether it is within a predetermined area on the main storage.

Abstract: A circuit for switching the source regions of reference devices used in a flash EPROM from ground potential to a potential of 3.5 volts during programming. This prevents charging of the floating gates of the reference devices on the selected word line and the discharging of the floating gates of the reference devices on the non-selected word lines.

Abstract: An Access List Entry Token (ALET) access look-aside facility is used to look at all entries in the access Look-Aside Buffer (ALB) and select a Segment Table Destination (STD) for use in Dynamic Address Translation (DAT). At the same time that address generation is done to form the virtual address used for DAT, the content of the access register (i.e., the ALET) to be used for the access is sent to the ALB. When the AR-specified STD is to be used for DAT, the ALET sent to the ALB is simultaneously compared with all the ALETs in the ALB. If the ALET compares with an ALET in an ALB entry, the STD associated with that entry is selected for use in the storage access.

Abstract: A method and apparatus for remapping of row addresses of memory requests to random access memory. A master device such as a central processing unit (CPU) issues a memory request comprising a memory address to the memory. The memory consists of multiple memory banks, each bank having a plurality of rows of memory elements. Associated with each memory bank is a sense amplifier latch which, in the present invention, functions as a row cache to the memory bank. The memory address issued as part of the memory request is composed of device identification bits to identify the memory bank to access, row bits which identify the row to access, and column address bits which identify the memory element within the row to access. When memory is to be accessed the row of data identified by the row bits is loaded into the sense amplifier latch and then is provided to the requesting master device.

Abstract: A data mechanism having a random access memory (RAM) which has a plurality of groups of memory chips, each group being divisible into two equally sized chip sets. Each group of memory chips is addressed by a first address and each individual memory chip is addressed by a second address. The random access memory contains stored data. A cache, connected to the RAM, stores a portion of data stored in the RAM and is accessed by a cache address for separately reading requested data therefrom. The cache provides a cache miss signal when it does not contain the requested data. A CPU, connected to the cache and the RAM, receives the cache miss signal and provides responsive thereto, a starting address to the random access memory for starting a block transfer from the random access memory to the cache in two shots. The starting address includes the first address and the second address.

Abstract: A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together using a boolean operation when generating the address. Using this method, the higher order register can be used to select a segment of the addressable space of the computer system. Then, all accesses to that portion of the addressable space can be controlled by changing only the lower order register. This results in a saving of time since only one of the registers need be reloaded for each subsequent access.

Abstract: In an address translation device having a main address translation unit (20) with a main access time that translates an input virtual address into a main real address, a subsidiary address translation unit (30) is connected to the main address translation unit (20). The subsidiary address translation unit (30) has a subsidiary access time shorter than the main access time and translates the input virtual address into a subsidiary real address. Connected to the main address translation unit (20) and the subsidiary address translation unit (30), an output address production unit (40) selectively produces one of the main real address and the subsidiary real address as an output real address. The subsidiary address translation unit (30) has an access/real address register (31) holding a buffer access address of the input virtual address and the main real address as a held access address and a held real address, respectively.

Abstract: A digital signal processor in which the control device transmits to and writes into the buffer memory the data necessary for multiplication or for generating addresses in the external memory, and then the data in the buffer memory is written into the internal memory during a single sampling period. This processing device contains an address comparator that compares the address set by the control device in the internal memory into which the data in the buffer memory is written, with the address in the internal memory controlled by the program, and then that produces control signals to write the data read from the buffer memory into the internal memory. The data read from the buffer memory is written into the internal memory, and is also used for multiplication or for generating addresses in the external memory.

Abstract: A memory mapping system for use by a port adapter in a computer facilitates access to named data buffers in host memory. The system generally comprises a mechanism that enables the adapter to efficiently translate the data buffer name to physical address locations in host memory without knowledge of the memory management policies of the computer. Specifically, the system includes various data structures and pointers that allow the port adapter to view host memory in "port pages" when accessing memory locations of a named data buffer. The data locations are virtually, but not physically, contiguous and the invention provides efficient identification of the physical addresses of the locations.

Abstract: The physical memory of a computer may not be directly accessable to the operator during the operation of a program due to the operational requirements of the operating system. Direct access to the physical memory of the computer during such operation may be possible through the aliasing of the physical memory locations and the creation of virtual alias addresses which will then give operator the necessary control to directly access any memory location thereby permitting the debugging of the program.

Abstract: Circuitry for overlapping a write access of a read-modify-write of a first bit with a subsequent read access of a second bit is described. The circuitry includes a latching circuit and a modify-write circuit. The latching circuit latches the active state of a select signal, which is used to select the SRAM cell storing the first bit during read and write accesses. The modify-write circuit modifies the first bit during the precharge preceding a read access of the second bit provided that it receives an active update write enable signal and an active signal from the latching circuit. Also described is a method of overlapping a read-modify-write cycle of a first SRAM bit with a subsequent read access of a second SRAM bit. The method begins by reading the first SRAM bit. Next, the second SRAM bit is precharged by bringing a precharge signal active. While the precharge signal is active the first SRAM bit is modified. Finally, the second SRAM bit is read after the precharge signal goes inactive.

Abstract: A circuit for repairing a defective memory cell between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.

Abstract: An apparatus for and method of loading the user addressing base register of a large scale multiprogrammed instruction processor. The base register is normally loaded to permit a user application program to access a different data segment. Providing a base register addressing environment for user application programs permits the software to be developed using virtual addressing. The addressing environment is specified by a stack of base registers. These are loaded from a data store specifying a virtual address for each data segment. During the loading process, an absolute address corresponding to the virtual address is loaded into each base register. To load a base register, a determination is made whether the future value differs from the previous value by a differential offset. If yes, the base register is loaded with an absolute address corresponding to the sum of the previous bank descriptor and the new offset. If no, the new base register value is computed by accessing a bank description table.

Abstract: A cache memory system for use during vector processing in a processor. The processor contains a central processing unit (CPU) and a main memory. The system includes a vector cache memory, a first address register, a main memory address calculation unit, and a cache address calculation unit. The first register stores a first address associated with an instruction executed by the CPU. The main memory address calculation unit is coupled to the first address register for calculating a second address utilizing the first address and vector stride data associated with said executed instruction. The second address is utilized to access the main memory. The cache address calculation unit is coupled to both the first address register and the main memory address calculation unit for calculating the third address utilizing portions of the first address and portions of the second address. The third address is utilized to access the vector cache memory.

Abstract: The data record copy apparatus for a virtual memory system instantaneously makes a copy of a selected data record by simply generating a new set of pointers to reference the same physical memory location as the original reference pointer. All the pointers referencing the same physical memory space are stored in the virtual memory mapping tables to record all the virtual addresses of the data record. When the original data record is staged to an associated cache memory or a copy of the data record is in cache memory, the consistency of the data record is maintained by loading all the virtual addresses of the data record from the mapping tables to the hash table and collision list of the cache memory. Thus, any access of one of these virtual addresses will result in the virtual memory system locating the single data record instance in cache memory.

Abstract: This invention relates principally to methods and apparatus for recording data on and reading data from a magnetizable medium using a scanning tunneling technique. Conventional rigid probes used in scanning tunneling microscopy (STM) and the like are replaced by a compliant magnetic probe wherein the STM image is a convolution of magnetic forces and the surface topography of the magnetizable medium. Data can be written to the medium by increasing the tunneling current, reducing the scan rate, and/or increasing the magnetization of the compliant magnetic tunneling tip in order to alter the local magnetic characteristics of the medium. A preferred material for the compliant probe is a free-standing thin film of iron vacuum-deposited on a glass substrate and later removed therefrom.The compliant probe of the invention may also be employed for imaging the local surface magnetization of a magnetic member.

Abstract: The memory addressing system of the present invention incorporates industry standard features for compatibility and adds the capability of using high-density module memory boards exclusively or in combination with current or next generation standard memory modules without increasing system power requirements. The system provides a plurality of standardized memory module circuit board sockets that are electrically connected so as to provide address decoded RAS signals in addition to the standard row and column addressing signals.