Patents Examined by Michael C Maskulinski
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Patent number: 10089204Abstract: A hierarchical fault detection and isolation system, method, and/or computer program product that facilitates fault detection and isolation in a complex networked system while reducing the computational complexity and false alarms is provided. The system, method, and/or computer program product utilizes a system level isolation and detection algorithm and a diagnostic tree to systematically isolate faulty sub-systems, components, etc. of the complex networked system.Type: GrantFiled: April 15, 2015Date of Patent: October 2, 2018Assignees: HAMILTON SUNDSTRAND CORPORATION, THE UNIVERSITY OF CONNECTICUTInventors: James Z. Hare, Shalabh Gupta, Nayeff A. Najjar, Paul M. D'Orlando, Rhonda Dawn Walthall
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Patent number: 10078564Abstract: As disclosed herein is a tool for preventing split-brain scenario, including determining, by a processor, that a first node of a HA cluster is unable to communicate with a second node of the HA cluster, and initiating, by a processor, by the first node, a handshake operation with a connected client, wherein the handshake operation comprises requesting that the client determine a status of the second node and receiving, from the client, a response indicating the status of the second node. Further, accepting, by a processor, new requests in response to determining that the second node is unavailable, and requesting, by a processor, restoration of communications between the first node and the second node in response to determining that the second node is available.Type: GrantFiled: December 5, 2017Date of Patent: September 18, 2018Assignee: International Business Machines CoporationInventors: Justin T. Fries, Timothy M. C. McCormick
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Patent number: 10078563Abstract: As disclosed herein is a tool for preventing split-brain scenario, including determining, by a processor, that a first node of a HA cluster is unable to communicate with a second node of the HA cluster, and initiating, by a processor, by the first node, a handshake operation with a connected client, wherein the handshake operation comprises requesting that the client determine a status of the second node and receiving, from the client, a response indicating the status of the second node. Further, accepting, by a processor, new requests in response to determining that the second node is unavailable, and requesting, by a processor, restoration of communications between the first node and the second node in response to determining that the second node is available.Type: GrantFiled: December 5, 2017Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: Justin T. Fries, Timothy M. C. McCormick
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Patent number: 10067813Abstract: In a method of analyzing a fault and/or error of an electronic system according to some example embodiments, a system call that accesses a hardware is replaced with a hooking system call including a code that executes the system call and a code that obtains monitoring information, the monitoring information including system call execution information and hardware performance information is obtained by executing the hooking system call when the hooking system call is called instead of the system call, and the monitoring information is recorded to analyze the fault/error of the electronic system based on the monitoring information.Type: GrantFiled: November 11, 2015Date of Patent: September 4, 2018Assignees: Samsung Electronics Co., Ltd., Ewha University-Industry Collaboration FoundationInventors: Jang-Hyuk An, Byoung-Ju Choi, Ji-Hyun Park
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Patent number: 10067833Abstract: A storage system according to the present invention comprises a controller and multiple storage devices, constitutes a RAID group from (n+m) number of storage devices, wherein the storage system stores write data from a host computer to n number of storage devices, and stores redundant data generated from the n number of data to m number of storage devices. When failure occurs to at least one storage device, the controller reads data in a compressed state and redundant data from each of the storage devices where failure has not occurred in the storage devices constituting the RAID group, and transmits the read data in the compressed state to the storage device which is a data recovery destination.Type: GrantFiled: July 31, 2014Date of Patent: September 4, 2018Assignee: Hitachi, Ltd.Inventor: Akira Matsui
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Patent number: 10013327Abstract: The present invention provides a monitor, especially a wake up monitor, for monitoring an integrated circuit, the monitor comprising a first monitoring unit configured to monitor at least one input of the integrated circuit, a second monitoring unit configured to monitor at least one output of the integrated circuit, a measurement unit configured to measure the time elapsed between an event on the at least one input and a reaction to the event on the at least one output and configured to output an alert signal if the elapsed time exceeds a predetermined first time limit. The present invention furthermore discloses an integrated circuit and a method for monitoring an integrated circuit.Type: GrantFiled: December 9, 2013Date of Patent: July 3, 2018Assignee: NXP USA, Inc.Inventors: Alistair Paul Roberston, Andrew Edward Birnie, Thomas Henry Luedeke
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Patent number: 8065559Abstract: The present invention provides methods and systems for performing load balancing via a plurality of virtual servers upon a failover using metrics from a backup virtual server. The methods and systems described herein provide systems and methods for an appliance detecting that a first virtual server of a plurality of virtual servers having one or more backup virtual servers load balanced by an appliance is not available, identifying at least a first backup virtual server of a one or more backup virtual servers of the first virtual server is available, maintaining a status of the first virtual server as available in response to the identification, obtaining one or more metrics from the first backup virtual server of a one or more backup virtual servers, and determining the load across the plurality of virtual servers using the metrics obtained from the first backup virtual server associated with the first virtual server.Type: GrantFiled: May 29, 2008Date of Patent: November 22, 2011Assignee: Citrix Systems, Inc.Inventors: Sandeep Kamath, Josephine Suganthi, Sergey Verzunov, Murali Raja, Anil Shetty
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Patent number: 8037361Abstract: Various method, system, and computer program product embodiments for implementing selective write-protect by a processor in a data storage system within a plurality of redundant storage systems for disaster recovery testing are provided. In one such embodiment, a write-protect state is initiated within at least one of the plurality of redundant storage systems. An available plurality of categories, including at least one write-protect exclusion category, is configured within a management interface of the data storage system, such that during the disaster recovery testing a storage volume categorized in the write-protect exclusion category is excluded from write protection.Type: GrantFiled: November 4, 2009Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Thomas W. Bish, Joseph M. Swingler
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Patent number: 8028198Abstract: Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input, and an address input. The command error module may be configured to detect an invalid command sequence and report an error indication to an output signal. Additionally, the memory device may include a temperature sensor operably coupled to a mode register and a reference voltage. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.Type: GrantFiled: July 30, 2007Date of Patent: September 27, 2011Assignee: Micron Technology, Inc.Inventor: David R. Resnick
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Patent number: 8001424Abstract: A system and method for mapping exceptions from a first programming model to a second programming model. The system comprises a first device operating a first programming model and a second device operating a second programming model. The first device sends an instruction to, or invokes the second device to execute an instruction. As a result, a fault occurs during execution of the instruction in the second programming model. An exception based on the fault is raised, and returned to the first device. A fault mapping module receives the exception from the first device. The fault mapping module attempts to determine the type of exception received by comparing an identifier with predetermined identifiers indicating exception type. The fault mapping module interprets the exception to generate an interpreted exception recognizable by the first programming model if the exception is determined to be of a predetermined type.Type: GrantFiled: February 11, 2010Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventor: Corville O. Allen
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Patent number: 8001421Abstract: A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point to the recovery block. A control flow edge is inserted from the recovery block to a entry point of the transaction. Checkpoint code is inserted before the entry point to backup live-in registers in backup storage elements and recovery code is inserted in the recovery block to restore the live-in registers from the backup storage elements in response to an abort of the transaction.Type: GrantFiled: August 13, 2010Date of Patent: August 16, 2011Assignee: Intel CorporationInventors: Cheng Wang, Youfeng Wu
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Patent number: 7996727Abstract: Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.Type: GrantFiled: June 25, 2010Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventor: William Henry Radke
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Patent number: 7996708Abstract: Techniques for file system resource restoration are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for file system resource restoration comprising modeling source configuration information of one or more file system resources associated with a first storage management system, modeling target configuration information of one or more file system resources associated with a second storage management system, mapping one or more portions of the source configuration information to the target configuration information, generating computer executable restoration instructions based at least in part on the mapping; and executing the computer executable restoration instructions to restore one or more file system resources of the source configuration information to a target computing platform identified by the target configuration information.Type: GrantFiled: March 16, 2009Date of Patent: August 9, 2011Assignee: Symantec CorporationInventor: Steven E. Mohl
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Patent number: 7992033Abstract: Corrective actions are managed for differing preferences among multiple sharing customers by a repository inquirer which, responsive to receipt of a fault event or out-of-limits condition for a shared resource of a first computing system domain, queries a customer requirements repository, determines affected application programs for the customers sharing the resource, determines affected customers on behalf of which affected application programs are being executed, and by a preference extractor which, responsive to the inquirer, extracts preferences for each affected application programs; and a corrective action instigator which, responsive to the extractor, performs two or more corrective actions according to the extracted preferences, wherein the corrective actions comprise at least two different actions, and wherein at least one corrective action comprises moving execution of an application program from a first computing system to a second computing system.Type: GrantFiled: March 27, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Rhonda L. Childress, Mark Anthony Laney, Reid Douglas Minyen, Neil Raymond Pennell
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Patent number: 7979748Abstract: A plurality of heap dump requests associated with an operating virtual machine (VM) program is received from a VM profiler interface module at a heap dump request processing module. In response to receipt of each heap dump request at the heap dump request processing module, a dynamic modifiable library identified within a dynamic modifiable configuration file is loaded into a memory, where the dynamic modifiable library comprises instructions associated with processing a current heap dump request. The instructions associated with processing the current heap dump request are executed. The dynamic modifiable library is unloaded from the memory. A plurality of heap dump files and a plurality of object movement event files generated by execution of the instructions are analyzed. A memory leak associated with the operating VM program is automatically identified based upon the analyzed plurality of heap dump files and the plurality of object movement event files.Type: GrantFiled: April 8, 2010Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventor: Michael J. Brady
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Patent number: 7979749Abstract: A method and infrastructure for a diagnosis and/or repair mechanism in a computer system, that includes an auxiliary service system running on the computer system.Type: GrantFiled: November 15, 2006Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Joefon Jann, Pratap Chandra Pattnaik, Ramanjaneya Sarma Burugula
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Patent number: 7975181Abstract: A device is disclosed for testing the function of a display port. The device includes a display port transmitting part, a field programmable gate array, and a memory. The display port transmitting part transmits connecting signals to a display port timing controller mounted on a display panel. The field programmable gate array applies a test signal to the display port timing controller, and controls the connecting signals applied from the display port transmitting part to the display port timing controller. The memory has software that determines acceptance or rejection of the display port function based on data output from the display port timing controller in response to the connecting signals or the test signal.Type: GrantFiled: March 31, 2009Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Taek-Young Kim
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Patent number: 7975167Abstract: An information system includes a housing with a plurality of units mounted thereon, a communication path built in the housing to take charge of information communication between a plurality of the units mounted on the housing, an information unit mounted on the housing to provide and process the information, a plurality of communication units each mounted on the housing to independently relay the information communication between the information unit and a device external to the housing, and a management unit for accessing the whole or a part of the plurality of the units mounted on the housing and acquiring internal information of the units accessed, wherein in the case where all the plurality of the communication units accessed are incommunicable, the internal information acquired from the plurality of the communication units is reported to the device external to the housing without passing through the plurality of the communication units.Type: GrantFiled: September 29, 2009Date of Patent: July 5, 2011Assignee: Fujitsu LimitedInventor: Masanori Takaoka
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Patent number: 7971100Abstract: A failure identification routine uses a two pass stack trace analysis in conjunction with a list of called types. As each method is called, a call list is generated with the called type, method, and various metadata. During the first pass stack trace analysis, each stack frame is analyzed to determine if the failed type is included in the stack frame. If so, the method associated with the frame is flagged as suspect. If the failed type is not found in the first stack trace, a second pass stack trace analysis is performed and an assembly associated with the method associated with the stack frame is analyzed to determine a set of types. The set of types are analyzed to find at least one match with the called types. If a match exists, the methods associated with the matched types are flagged as suspect.Type: GrantFiled: January 22, 2008Date of Patent: June 28, 2011Assignee: Microsoft CorporationInventors: Rafael Goodman Dowling, Ryan Randal Elliott, Israel Hilerio
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Patent number: 7966514Abstract: A fault tolerant system for a highly scalable distributed processing system in which fault tolerant groups (hereafter referred to as “FT groups”) are formed based on the functionalities of applications. A given FT group includes instances of the same applications and also different applications that perform the same function. The instances within the FT group are ranked as a primary and mirrors, which descend in rank. When the primary instance in the FT group crashes, that is, fails or becomes otherwise unavailable, the system utilizes the next ranking available (running) instance in the FT group as the primary instance. The change over to the next ranking mirror application is performed quickly and without loss of functionality through an exchange of “FT messages” under the control of a central monitoring and change-over control sub-system.Type: GrantFiled: September 19, 2006Date of Patent: June 21, 2011Assignee: Millennium IT (USA), Inc.Inventor: Lakshitha C. Surasinghe