Abstract: A method and system for storing data in portable storage devices. Specifically, the disclosed method and system provide a solution for the write-hole problem inflicting persistent storage, especially redundant array of independent disks (RAID) configured storage. The write-hole problem may arise from the occurrence of power failure during a write operation of data to RAID configured storage, subsequently resulting in disparities between the data and parity information thereof—the consistency there-between of which is critical to data reconstruction upon disk failure. To rectify these inconsistencies, a full-stripe (or full-block set) write is recommended, which the disclosed method and system implements through the use of, and re-mapping of relationships between, virtual, physical, and in-memory block sets.

Abstract: A memory module includes register selection logic to select alternate local source and/or destination registers to process PIM commands. The register selection logic uses an address-based register selection approach to select an alternate local source and/or destination register based upon address data specified by a PIM command and a split address maintained by a memory module. The register selection logic may alternatively use a register data-based approach to select an alternate local source and/or destination register based upon data stored in one or more local registers. A PIM-enabled memory module configured with the register selection logic described herein is capable of selecting an alternate local source and/or destination register to process PIM commands at or near the PIM execution unit where the PIM commands are executed.

Abstract: Systems, apparatuses, and methods for efficiently processing memory requests are disclosed. A computing system includes at least one processing unit coupled to a memory. Circuitry in the processing unit determines a memory request becomes a long-latency request based on detecting a translation lookaside buffer (TLB) miss, a branch misprediction, a memory dependence misprediction, or a precise exception has occurred. The circuitry marks the memory request as a long-latency request such as storing an indication of a long-latency request in an instruction tag of the memory request. The circuitry uses weighted criteria for scheduling out-of-order issue and servicing of memory requests. However, the indication of a long-latency request is not combined with other criteria in a weighted sum. Rather, the indication of the long-latency request is a separate value. The circuitry prioritizes memory requests marked as long-latency requests over memory requests not marked as long-latency requests.

Abstract: A method includes updating a first metadata log in an NVRAM of a host device corresponding to one or more recent input/output (I/O) operations received by the host device, periodically checking whether the size of the updated first metadata log is greater than a flush limit maintained in the host device, triggering a meta flush thread when the updated first metadata log size exceeds the flush limit maintained in the host device, sending, by a non-volatile memory express (NVMe) driver, a first command for synchronizing the updated first metadata log to one or more solid state drives (SSDs) for updating a second metadata log in the one or SSDs, and discarding, by the host device, metadata of the first metadata log updated in the host device after receiving a second command for acknowledging synchronization completion from the one or more SSDs.

Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

Abstract: A system, method and device for ingesting data files into remote computing environments is disclosed. The method includes receiving a plurality of data files and processing same according to a modified round-robin (MRR) process. The MRR assigns data files for processing by determining which of a plurality of remote processors are active, and by determining an amount of queued processing for the active remote processors. The method includes assigning each data file of the plurality of data files to a remote processor of the plurality of remote processors based on the remote processor (1) being active, and (2) having a relatively lower amount of queued processing. The method includes instructing a storage writer to store processed data files.

Abstract: A data storage device and method for detecting malware on a data storage device. The device includes a non-volatile storage medium configured to store at least one file system control block and user data block(s) to store user data. The file system control block comprises at least one reference data structure. The data storage device further comprises a buffer to temporarily store user data. The data storage device further comprises a controller to scan each write command in the user data to be transferred for protocol commands or malicious data. The controller also stops the data transfer of user data from the buffer to the non-volatile storage medium if at least one of protocol commands or malicious data is detected in at least one write command.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.

Abstract: A memory access command to be performed on a die of a memory device is received, wherein the memory access command comprises a base partition number and a base page address. The memory access command is converted into a plurality of commands based on a number of partitions associated with the die. A respective partition number derived from the base partition number is determined for each command of the plurality of commands. A respective page address associated with each command of the plurality of commands is determined using the base page address. The plurality of commands is executed using, for each command of the plurality of commands, the respective partition number and the respective page address.

Abstract: Systems, apparatuses, and methods for memory management are described. For example, these may include a first memory level including memory pages in a memory array, a second memory level including a cache, a pre-fetch buffer, or both, and a memory controller that determines state information associated with a memory page in the memory array targeted by a memory access request. The state information may include a first parameter indicative of a current activation state of the memory page and a second parameter indicative of statistical likelihood (e.g., confidence) that a subsequent memory access request will target the memory page. The memory controller may disable storage of data associated with the memory page in the second memory level when the first parameter associated with the memory page indicates that the memory page is activated and the second parameter associated with the memory page is greater than or equal to a threshold.

Abstract: A computer-implemented method for unoptimized tape drive read detection is disclosed. The computer-implemented includes determining whether a read order of a trio of related files is consistent with an order in which the trio of related files are stored on a magnetic tape media. The computer-implemented method further includes generating an unoptimized tape drive read warning in response to determining that the read order of the trio of related files is inconsistent with the order in which the trio of related files are stored on the magnetic tape media.

Abstract: A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.

Abstract: A method for updating stored information and an apparatus. A controller performs error correction code (ECC) decoding on stored data information based on the stored data information and stored ECC check information to generate an error-corrected codeword, where the error-corrected codeword includes error-corrected data information. The controller generates candidate to-be-written data information based on the error-corrected data information and a data update indication. The controller performs a mask operation on the candidate to-be-written data information based on the stored data information, and writes unmasked content in the candidate to-be-written data information into a memory.

Abstract: Embodiments include methods, systems and computer program products for managing a flash memory device. Aspects include monitoring a percentage of memory of the flash memory device that is in a ready to use state. Aspects also include operating the flash memory device in a first operating mode based on a determination that the percentage is greater than a first threshold value. Aspects further include operating the flash memory device in a second operating mode based on a determination that the percentage has fallen below the first threshold value. Aspects include operating the flash memory device in a third operating mode until the percentage exceeds the first threshold value based on a determination that the percentage has fallen below a second threshold value, which is lower than the first threshold value. The erasing of ready to erase memory block stripes is only performed during the third operating mode.

Abstract: In some aspects, a non-transitory computer readable storage medium includes instructions stored thereon that, when executed by a processor, cause the processor to create a virtual swap space that is exposed to a core system software, intercept a first page selected by the core system software to be swapped out to the virtual swap space, map the virtual swap space to a physical swap space that is allocated to a type of page associated with first swap metadata, and write the first page to the physical swap space based on the first page having the first swap metadata. In some embodiments, the first page is associated with the first swap metadata.

Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

Abstract: Embodiments are described for storing array snapshots of a block-based system in networked storage, such as an NAS or SAN device. A system and process determines a size of the block device and splits it into a number of slices based on the size of the block device, with each slice comprising slice data. The slice data is written to protection storage either directly or through temporary buffer memory. The slice number and memory location for the slice data is stored in a key/value map, where the key comprises the slice number, and the value comprises the location. Backup agents are deployed to back up the slice data for each slice of the block device to the networked storage, and the slice data is stored as array snapshots in the network storage.

Abstract: A data storage server may store a data packet generated by a client in a first server memory prior to the data packet being migrated to a third server memory of the data storage server by a server controller in response to a server data migration module. The data packet may be moved to satisfy a quality of service agreement between a host and the client. The data packet can be proactively copied to a second server memory by the server controller in response to the migration of the data packet from the first to the third server memories.

Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.

Abstract: Methods, systems, and devices for temperature-based scrambling for error control in memory systems are described. Techniques are described for a memory system to scramble data using different scrambling code parameters when writing the data at different temperatures. Scrambling the data using scrambling code parameters that are based on the temperatures at the time or writing the data may reduce errors introduced into the data by operating the memory cells at extreme temperatures.