Patents Examined by Michael Krofcheck
  • Patent number: 11886751
    Abstract: Embodiments are described for storing array snapshots of a block-based system in networked storage, such as an NAS or SAN device. A system and process determines a size of the block device and splits it into a number of slices based on the size of the block device, with each slice comprising slice data. The slice data is written to protection storage either directly or through temporary buffer memory. The slice number and memory location for the slice data is stored in a key/value map, where the key comprises the slice number, and the value comprises the location. Backup agents are deployed to back up the slice data for each slice of the block device to the networked storage, and the slice data is stored as array snapshots in the network storage.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 30, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Adam Brenner, Upanshu Singhal
  • Patent number: 11886732
    Abstract: A data storage server may store a data packet generated by a client in a first server memory prior to the data packet being migrated to a third server memory of the data storage server by a server controller in response to a server data migration module. The data packet may be moved to satisfy a quality of service agreement between a host and the client. The data packet can be proactively copied to a second server memory by the server controller in response to the migration of the data packet from the first to the third server memories.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 30, 2024
    Assignee: Seagate Technology LLC
    Inventors: Paul F. Kusbel, John E. Moon
  • Patent number: 11880309
    Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 23, 2024
    Assignee: VMware, Inc.
    Inventors: Nishchay Dua, Andreas Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Venkata Subhash Reddy Peddamallu, Adarsh Seethanadi Nayak
  • Patent number: 11875039
    Abstract: Methods, systems, and devices for temperature-based scrambling for error control in memory systems are described. Techniques are described for a memory system to scramble data using different scrambling code parameters when writing the data at different temperatures. Scrambling the data using scrambling code parameters that are based on the temperatures at the time or writing the data may reduce errors introduced into the data by operating the memory cells at extreme temperatures.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Joseph Bueb
  • Patent number: 11868626
    Abstract: A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongin Lee, Doogie Lee
  • Patent number: 11861189
    Abstract: A memory system includes a memory device including a plurality of memory blocks, each memory block including memory cells capable of storing multi-bit data, and a controller configured to allocate the plurality of memory blocks for plural zoned namespaces input from an external device and access a memory block allocated for one of the plural zoned namespaces which is input along with a data input/output request. In response to a first request input from the external device, the controller adjusts a number of bits of data stored in a memory cell included in a memory block, which is allocated for at least one zoned namespace among the plural zoned namespaces, and fixes a storage capacity of the at least one zoned namespace.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: January 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Duk Joon Jeon
  • Patent number: 11847346
    Abstract: A method, computer program product, and computing system for receiving data for storage in a storage system. The data may be written to a head entry of a log buffer, wherein the log buffer includes a plurality of data entries for flushing to the storage system. At least a portion of the plurality of data entries of the log buffer may be flushed, via a plurality of threads, to the storage system based upon, at least in part, a tail entry of the log buffer. A queue of committed data entries may be updated, via each thread of the plurality of threads, with one or more data entries of the log buffer flushed to the storage system by each thread. A new tail entry of the log buffer may be determined, via a thread of the plurality of threads, based upon, at least in part, the queue of committed data entries.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: December 19, 2023
    Assignee: EMC IP Holding Company, LLC
    Inventors: Nimrod Shani, Ronen Gazit, Uri Shabi
  • Patent number: 11842074
    Abstract: A method for striping, the method may include performing, for each period of time out of multiple periods of time, the steps of: (i) determining striping rules; wherein the determining of the striping rules may include selecting one or more selected stripe size values out of multiple stripe size value candidates; wherein the selecting is based on values of storage system parameters that are obtained when applying the multiple stripe size value candidates; wherein the storage system parameters comprise storage space utilization and storage system throughput; and (ii) applying the striping rules by the storage system, during the period of time; wherein the applying comprises obtaining data chunks; converting the data chunks to stripes having at least one of the one or more selected stripe size values; and storing the stripes in the storage system.
    Type: Grant
    Filed: March 21, 2021
    Date of Patent: December 12, 2023
    Assignee: VAST DATA LTD.
    Inventors: Yogev Vaknin, Eli Malul, Lior Klipper, Renen Hallak
  • Patent number: 11829609
    Abstract: A secondary storage controller determines one or more tracks of one or more volumes in which data loss has occurred in the secondary storage controller. The secondary storage controller suspends a peer to peer remote copy operation between the secondary storage controller and a primary storage controller. Information on the one or more tracks of the one or more volumes in which the data loss has occurred is transmitted to the primary storage controller.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: November 28, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew D. Carson, Carol S. Mellgren, Karl A. Nielsen, Matthew Sanchez, Todd C. Sorenson
  • Patent number: 11829635
    Abstract: Managing a memory element of a memory module, including identifying a PPR listing for the memory element that is stored at a SPD of the memory module; identifying an event associated with a memory address location of the memory element during runtime of the memory module and in response accessing the SPD to write data to the PPR listing indicating the memory address location of the memory element associated with the event; determining whether the PPR listing has available space to store the data indicating the memory address location of the memory element associated with the event; determining that the PPR listing has available space to store the data indicating the memory address location of the memory element associated with the event, and in response, storing the data indicating the memory address location of the memory element associated with the event at the PPR listing at the SPD.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: November 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Kevin M. Cross, Jordan Chin, Isaac Qin Wang
  • Patent number: 11829648
    Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: November 28, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11809282
    Abstract: A deduplication pipeline method to enable shorter overall latency, servicing of multiple calls in parallel, and implementing higher data compression ratio. The method includes receiving user data for storage, performing deduplication operation on the data to obtain non-duplicative data, buffering the non-duplicative data in persistent memory, and accepting next user data for deduplication processing. In parallel to receiving the next user data, operating a co-processor to asynchronously compressing the data stored in the persistent memory and storing the compressed data in RAID.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 7, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Shuguang Gong, Yong Zou, Jet Chen
  • Patent number: 11803487
    Abstract: Techniques for transitioning between memory segment views include: instantiating a first memory segment view that confines access to a memory segment to a first thread; receiving a request to transition ownership of the memory segment to a second thread; responsive to receiving the request to transition ownership of the memory segment to the second thread: instantiating a second memory segment view that permits access to the memory segment by the second thread; copying metadata from the first memory segment view to the second memory segment view; terminating the first memory segment view, to prevent access to the memory segment via the first memory segment view.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: October 31, 2023
    Assignee: Oracle International Corporation
    Inventors: Maurizio Cimadamore, James Malcolm Laskey, Jorn Bender Vernee
  • Patent number: 11803483
    Abstract: Example implementations relate to storing manifest portions in a metadata cache. An example includes receiving, by a storage controller, a read request associated with a first data unit. In response to receiving the read request, the storage controller stores a manifest portion in a metadata cache, the stored manifest portion comprising a plurality of records, the plurality of records including a first record associated with the first data unit. The storage controller determines storage information of the first data unit using pointer information included in the first record of the stored manifest portion, and replaces the pointer information in the first record with the determined storage information of the first data unit.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: October 31, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Richard Phillip Mayo, David Malcolm Falkinder, Peter Thomas Camble
  • Patent number: 11797444
    Abstract: There are provided a storage device and an operating method thereof. The storage device includes: a memory device including a plurality of memory blocks, a buffer memory configured to temporarily store data, and a memory controller configured to, in response to occurrence of a power loss, generate address information including logical addresses of write data that correspond to the data temporarily stored in the buffer memory and meta data, and control the memory device to store the address information and the write data in a predetermined backup block group included in the plurality of memory blocks.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventor: Jae Il Lee
  • Patent number: 11797199
    Abstract: A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: October 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Roman Alexander Pletka, Aaron Daniel Fry, Nikolaos Papandreou, Radu Ioan Stoica, Charalampos Pozidis, Nikolas Ioannou
  • Patent number: 11789612
    Abstract: For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: October 17, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Karin Inbar, Sahil Sharma, Grishma Shah
  • Patent number: 11789631
    Abstract: A method includes receiving data for storage and encoding the data to produce a plurality of data slices. Metadata is determined for a data slice of the plurality of data slices. The metadata is stored in a metadata storage tree. The metadata storage tree is stored via a first plurality of memory devices of a first memory type. The data slice is stored in a slice storage location in a second plurality of memory devices of a second memory type. The slice storage location is indicated by the metadata. The first memory type has a higher performance level than the second memory type based on a utilization approach.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Renars W. Narubin, Jason K. Resch, Gary W. Grube
  • Patent number: 11789623
    Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: October 17, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Ian King
  • Patent number: 11789870
    Abstract: The described technologies enable a computing device to allocate at least a portion of its persistent memory as volatile memory during runtime. At least some implementations create a file in the persistent memory of the computing device. The file is created in the persistent memory of the computing device during runtime of a virtual machine (VM) hosted by the computing device. The file may be allocated to the VM. The file allocated to the VM may be used as volatile memory. For example, the VM may use the file to store temporary data (e.g., volatile data). In some implementations, the temporary data is associated with an application executing in the VM.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 17, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Neal Robert Christiansen, Scott Chao-Chueh Lee