Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: An organic light-emitting display device including a substrate; a pixel in a display area of the organic light-emitting display device, the pixel being implemented by an organic light-emitting diode on the substrate; a first inclination structure surrounding the pixel; a second inclination structure at least partially surrounding the first inclination structure; and a planarization layer covering the first inclination structure and the second inclination structure and having a refractive index that is greater than a refractive index of the first inclination structure and is greater than a refractive index of the second inclination structure, wherein a height of the first inclination structure is greater than a height of the second inclination structure.

Abstract: The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen. The disclosed techniques form an APT specimen or sample directly on a DUT region on a wafer. The APT specimen is formed integrally to the substrate or the support structure, e.g., a carrier, under the APT specimen. A laser patterning is conducted to form a trench in the DUT and one or more bump structures in the trench. The laser patterning is relatively coarse and forms a coarse surface texture on each of the bump structures. A low-kV gas ion milling using a dual-beam focused ion beam (“FIB”) microscopes is then conducted to shape the bump structures into APT specimen.

Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.

Abstract: A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.

Abstract: An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g.

Abstract: Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.

Abstract: A method of fabricating an IC includes forming a layer stack thereon including silicon nitride layer on a first silicon oxide layer, with a second silicon oxide layer thereon on a substrate including a semiconductor material. The layer stack is etched to form ?1 trench that is at least 2 microns deep into the semiconductor material. A dielectric liner is formed on sidewalls and a bottom of the trench. A polysilicon layer is formed on the dielectric liner that fills the trench and extends lateral to the trench. Chemical mechanical planarization (CMP) processing stops on the silicon nitride layer to remove the polysilicon layer and the second silicon oxide layer to form a trench structure having a polysilicon fill. After the CMP processing, thermal oxidation oxidizes exposed regions of the polysilicon layer to form a polysilicon oxide layer. After the thermal oxidizing, the silicon nitride layer is removed.

Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.

Abstract: Disclosed is a semiconductor device comprising: a substrate; a vertical active region formed on the substrate and comprising a first source/drain region, a channel region, and a second source/drain region sequentially disposed in a vertical direction, the first source/drain region including a laterally extending portion extending beyond a portion of the active region above the laterally extending portion; a gate stack formed around the periphery of the channel region, the gate stack including a laterally extending portion; and a stack contact portion from above the laterally extending portion of the first source/drain region to the laterally extending portion of the first source/drain region. The stack contact portion comprises a three-layer structure sequentially disposed in the vertical direction: a lower layer portion, a middle layer portion, and an upper layer portion.

Abstract: A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

Abstract: A display panel and a display device are provided. The display panel includes a plurality of light emitting points; a plurality of pixel driving circuits, wherein at least one of the plurality of light emitting points is connected to at least one of the plurality of pixel driving circuits; and a plurality of electrode leads, the at least one of the plurality of light emitting points is connected to the at least one of the plurality of pixel driving circuits through at least one of the plurality of electrode leads; the plurality of pixel driving circuits are separated from the plurality of light emitting points.

Abstract: The embodiments of the present application provide a display substrate, a light field display apparatus, and a method for driving the same. The display substrate includes: a base substrate; a light emitting block on the base substrate, wherein the light emitting block includes a plurality of first light emitting units, and each of the first light emitting units includes a plurality of first light emitting points which are located at a plurality of predetermined positions in the first light emitting unit respectively; and first driving leads each electrically connected to first light emitting points located at the same predetermined positions in the respective first light emitting units and configured to receive a first driving signal from a driving circuit.

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

Abstract: A method of microfabrication includes providing a substrate having a first layer including a first semiconductor material. A second layer of a second semiconductor material is formed over the first layer. The second layer is directionally etched using a mask to form independent core structures of the second semiconductor material on the first semiconductor material. A third layer of a first dielectric material is formed on an exposed surface of the first layer to cover a lower portion of a respective sidewall of each core structure. A shell structure is formed on an upper portion of a respective sidewall of each core structure to form shell structures including at least one semiconductor material. The core structures are removed such that each shell structure forms a vertical semiconductor structure extending vertically from the first layer and electrically isolated from the first semiconductor material by the first dielectric material.

Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

Abstract: A display device includes: a light-emitting element at a display area; a driving element electrically connected to the light-emitting element; an encapsulation layer covering the light-emitting element; a touch sensor on the encapsulation layer; a connection pad at a bonding area, the connection pad including a lower conductive layer, an intermediate conductive layer on the lower conductive layer, and an upper conductive layer on the intermediate conductive layer; a cladding layer covering at least a side surface of the intermediate conductive layer and including an organic material; a passivation layer covering an upper surface of the cladding layer and including an inorganic material, a portion of the passivation layer being located under the upper conductive layer; and a driving circuit attached to the connection pad.