Patents Examined by Michael R. Fleming
  • Patent number: 5287432
    Abstract: Fuzzy control is disclosed in the environment of tracking control for a playback head relative to a medium from which signals are played back. Tracking control data is generated as a function of the detected signal level of the played back signal by using fuzzy inference to obtain direction and magnitude values of the control data which then is used to adjust the tracking of the head. Membership functions for tracking control signals are represented as a set of equivalent triangles and are provided as identifying data characterizing the shape of a membership function and position data locating the respective position of each membership function along the abscissa.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: February 15, 1994
    Assignee: Sony Corporation
    Inventor: Tadafusa Tomitaka
  • Patent number: 5287523
    Abstract: A method for servicing peripheral interrupt requests in a data processing system is provided. A state vector register stores a current state of a state machine which controls the interrupt-generating peripheral. In addition, the state vector register simultaneously stores an interrupt source identifier, which indicates the source of the highest priority interrupt request currently pending for the interrupt-generating peripheral. When the processor receives an interrupt request, the value stored in the state vector register of the interrupt-generating peripheral is read into an index register in the processor. The processor then uses the value as an index into a jump table, stored in memory, which contains the interrupt service routines. The use of the state vector register in conjunction with existing internal signals enables the processor to rapidly retrieve the appropriate interrupt service routine from memory, while minimizing the system overhead associated with servicing the interrupt request.
    Type: Grant
    Filed: October 9, 1990
    Date of Patent: February 15, 1994
    Assignees: Motorola, Inc., Ford Motor Company
    Inventors: Nigel J. Allison, Janice L. Benzel, Joseph F. Kowalski
  • Patent number: 5287429
    Abstract: On carrying out connected word recognition in compliance with a regular grammar and in synchronism with successive specification of input feature vectors of an input pattern, one of an n-th word (n) of first through third occurrence (n(1) to n(3)) is selected as the n-th word of selected occurrence in an i-th period in which an n-th input feature vector is specified. The n-th word appears as the first through the third occurrence in transition rules specified by the grammar. In the i-th period, distances are calculated, only for the n-th word of the selected occurrence, between the input feature vector assigned to the i-th period and reference feature vectors for the n-th word.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: February 15, 1994
    Assignee: NEC Corporation
    Inventor: Takao Watanabe
  • Patent number: 5287433
    Abstract: To perform a simple and rapid preparation of control program, the control device for a robot manipulator for a sheet metal bending installation is provided with a first key for inputting a command signal for actuating a first actuator that is adapted to move a movable element of the metal sheet bending installation through a constant distance or amount, and a second key for inputting a command signal for actuating a second actuator that is adapted to move another movable element of the metal sheet bending installation through a changeable distance or amount.
    Type: Grant
    Filed: August 7, 1991
    Date of Patent: February 15, 1994
    Assignee: Amada Company Limited
    Inventors: Gianpaolo Prunotto, Marco Prada
  • Patent number: 5285522
    Abstract: A machine for neural computation of acoustical patterns for use in real-time speech recognition, comprising a plurality of analog electronic neurons connected for the analysis and recognition of acoustical patterns, including speech. Input to the neural net is provided from a set of bandpass filters which separate the input acoustical patterns into frequency ranges. The neural net itself is organized into two parts, the first for performing the real-time decomposition of the input patterns into their primitives of energy, space (frequency) and time relations, and the second for decoding the resulting set of primitives into known phonemes and diphones. During operation, the outputs of the individual bandpass filters are rectified and fed to sets of neurons in an opponent center-surround organization of synaptic connections ("on center" and "off center"). These units compute maxima and minima of energy at different frequencies.
    Type: Grant
    Filed: October 8, 1991
    Date of Patent: February 8, 1994
    Assignee: The Trustees of The University of Pennsylvania
    Inventor: Paul H. Mueller
  • Patent number: 5285521
    Abstract: A method and apparatus for utilizing the sound and pattern recognition capabilities of the human auditory system, which takes information contained in typical instrumentation signals in the form of amplitude, frequency, and time characteristics, and converts this information into sound qualities and characteristics which are recognizable by the human listener. The method and apparatus digitizes the analog amplitude, frequency, and time information, and selects appropriate sound characteristics into which it may encode this information in standardized form that is recognizable to the human listener. The method allows for the testing or inspection of materials using nondestructive evaluation techniques in a manner that allows the tester to interpret the information provided by the testing system, either exclusively through his auditory senses, or through his auditory senses in conjunction with visual indicators.
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: February 8, 1994
    Assignee: Southwest Research Institute
    Inventors: Amos E. Holt, Kent D. Polk, Richard A. Cervantes
  • Patent number: 5283857
    Abstract: A new expert system performs a redesign in connection with an original design. The expert system comprises a discrepancy determination component that identifies a discrepancy between operation of the original design and a desired operation. A redesign component including at least one redesign module associated with a discrepancy generates a redesign in response to the original design and the identified discrepancy. Finally, a redesign generation component generates a redesign module in response to a previously-identified discrepancy and design, the redesign module thereafter being used by the redesign component.
    Type: Grant
    Filed: January 8, 1993
    Date of Patent: February 1, 1994
    Assignee: Digital Equipment Corporation
    Inventor: Evangelos Simoudis
  • Patent number: 5283905
    Abstract: A power supply for a computer system manager, wherein the power supply has its own secondary power source operable when input power to the system manager no longer meets preset threshold values. The power supply functions in one of a discrete number of power modes depending upon the amount of energy available from either the computer input power or the secondary power source. The power supply switches to one of the group of power modes to conserve secondary power when the computer input power is no longer available. The power modes are controlled by a power mode controller which selectively directs power to discrete components of the system manager as a power conservation technique. The power mode controller always energizes the random access memory of the system manager in order to maintain data integrity.
    Type: Grant
    Filed: June 24, 1991
    Date of Patent: February 1, 1994
    Assignee: Compaq Computer Corporation
    Inventors: Said S. Saadeh, Paul R. Fulton, Thomas J. Hernandez, Arthur D. Heald, Richard A. Stupek
  • Patent number: 5283856
    Abstract: A flexible, event driven and conditional rule based mail messaging system which can be transparently implemented for use in electronic mail applications. A rule mechanism is implemented having a "When-If-Then" event-driven, conditional, action-invoking paradigm or "triplet" which permits definition of a repertoire of events considered to be significant events upon which to trigger actions in the electronic mail messaging system. Each particular event may be associated with a specific mail message and/or rules to promote efficient mapping of messages, events and rules so that only rules associated with a specific event are invoked upon occurrence of the event. Only relevant rules, i.e. those associated with a satisfied event, need be further processed. A graphical user interface to a structured rule editor facilitates synthesis of rules by a user via a substantially transparent rule engine.
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: February 1, 1994
    Assignee: Beyond, Inc.
    Inventors: Kevin C. Gross, Charles J. Digate, Eugene H. Lee
  • Patent number: 5282272
    Abstract: A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to processor directed interrupt requests, processor to one processor of a group of processors interrupt requests, and processor to all processors of a group of processors interrupt requests.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: January 25, 1994
    Assignee: Intel Corporation
    Inventors: Charles B. Guy, Sudarshan B. Cadambi, Michael J. Gutmann, Narjala Bhasker, Jim R. Trethewey, Brian J. McArdle
  • Patent number: 5280616
    Abstract: In a logic circuit having clocked state latches and combinatorial logic for functional processing of a task in response to functional clocking of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic is provided for suspending task processing by interrupting the functional clocking of the state latches and, during such suspension, scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performed by a logic circuit in a multiprocessing enviornment.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: January 18, 1994
    Assignee: International Business Machines Corporation
    Inventors: Nicholas D. Butler, Malcolm D. Buttimer, Brian C. Homewood, Steven P. Larky, Roderick M. West, Paolo G. Sidoli
  • Patent number: 5280624
    Abstract: A circuit structure for calculating a fuzzy inference for a fuzzy logic controller is disclosed in which a memory unit is divided into a first memory for storing a plurality of membership functions whose number corresponds to the number of fuzzy levels for respective input variables and into a second memory for storing a plurality of encoded fuzzy control linguistic rules. Then, the fuzzy levels in the form of grades are integrally accessed for the respective input variables into a plurality of registers together with the encoded fuzzy control linguistic rules so that the registers prepare the synthesized data of the fuzzy levels and membership functions in the one of the linguistic rule.
    Type: Grant
    Filed: January 31, 1992
    Date of Patent: January 18, 1994
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Hiroshi Ikeda
  • Patent number: 5280562
    Abstract: In speech recognition and speech coding, the values of at least two features of an utterance are measured during a series of time intervals to produce a series of feature vector signals. A plurality of single-dimension prototype vector signals having only one parameter value are stored. At least two single-dimension prototype vector signals having parameter values representing first feature values, and at least two other single-dimension prototype vector signals have parameter values representing second feature values. A plurality of compound-dimension prototype vector signals have unique identification values and comprise one first-dimension and one second-dimension prototype vector signal. At least two compound-dimension prototype vector signals comprise the same first-dimension prototype vector signal. The feature values of each feature vector signal are compared to the parameter values of the compound-dimension prototype vector signals to obtain prototype match scores.
    Type: Grant
    Filed: October 3, 1991
    Date of Patent: January 18, 1994
    Assignee: International Business Machines Corporation
    Inventors: Lalit R. Bahl, Jerome R. Bellegarda, Edward A. Epstein, John M. Lucassen, David Nahamoo, Michael A. Picheny
  • Patent number: 5280563
    Abstract: In a continuous speech recognizer which includes at least, one acoustic expert and one linguistic expert which generate respective scores, a method is disclosed for adjusting the relative weighting to be applied to those scores employing training data utilizing the words to be recognized in multiple word phrases. Multiple word test phrases are applied to the acoustic expert to determine, for each phrase, plural multi-word hypotheses each having corresponding cumulative scores. The linguistic expert generates corresponding cumulative linguistic scores. An objective function is calculated for each test phrase having a value which is variable as a function of the difference between the combined score of any correct hypothesis and that of the most easily confused incorrect hypothesis. The objective function values are cumulated and a gradient descent procedure is used to adjust the relative weighting of the acoustic and linguistic scores in obtaining a combined score.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: January 18, 1994
    Assignee: Kurzweil Applied Intelligence, Inc.
    Inventor: William F. Ganong
  • Patent number: 5280564
    Abstract: The characteristic data for determining the characteristics of the transfer functions (for example, sigmoid functions) of the neurons of the hidden layer and the output layer (the gradients of the sigmoid functions) of a neural network are learned and corrected in a manner similar to the correction of weighting data and threshold values. Since at least one characteristic data which determines the characteristics of the transfer function of each neuron is learned, the transfer function characteristics can be different for different neurons in the network independently of the problem and/or the number of neurons, and be optimum. Accordingly, a learning with high precision can be performed in a short time.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: January 18, 1994
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Kazuyuki Shiomi, Sei Watanabe
  • Patent number: 5280585
    Abstract: Disclosed is a switch that allows a peripheral device, such as a PCL printer, to be shared by multiple computer systems. The switch connects to each of the computer systems, and also to the peripheral device being shared. The first system is considered the primary user of the peripheral device, so when the second system requests access to the peripheral device, the switch causes the peripheral device to save its state temporarily while the second system uses the device. When the second system's use is complete, the switch causes the peripheral device to restore its state to the last state established by the first system. Therefore, the first system need not know that the other system used the peripheral device, since the state of the peripheral device appears unchanged from the last time the first system used the device.
    Type: Grant
    Filed: September 28, 1990
    Date of Patent: January 18, 1994
    Assignee: Hewlett-Packard Company
    Inventors: Richard L. Kochis, Michael D. Erickson
  • Patent number: 5280587
    Abstract: A computer system includes a bus and a plurality of devices coupled to the bus. A CPU within the bus controller generates addresses for data transfers to and from the devices. A bus controller generates control signals for the data transfers. A data transfer rate controlled by the control signals is varied so that the data transfer rate is optimal for data transfers to and from each device. The data transfer rate for a data transfer to or from a first device is based on a subset of address bits used by the CPU to address the first device.
    Type: Grant
    Filed: March 31, 1992
    Date of Patent: January 18, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Ataru Shimodaira, Walter H. Potts
  • Patent number: 5280565
    Abstract: A sequential type Fuzzy backward reasoning device is disclosed, which is capable of performing computation progressing every time a feature quantity is observed to update reasoning and of performing the reasoning even if the order of observations is arbitrary, by providing means for performing sequential reasoning instead of batch type reasoning means, and feedback means for feeding back a reasoned result.Additionally, a target recognition device is disclosed which is capable of computing as a numerical value the reliable degree of a recognized result on a target by obtaining another recognizing information even if there is not obtained any information concerning the target, using said sequential type Fuzzy backward reasoning device.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: January 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohei Nomoto, Tetsuo Kirimoto, Yoshimasa Ohhashi
  • Patent number: 5280590
    Abstract: A support chip includes substantially all the AT core logic, namely most of the X-bus peripherals (except for the keyboard controller), memory controllers, and swapper. The normal AT data paths are altered to reduce the pin count, with a resulting surprising improvement in capability. The chip interfaces to the microprocessor's local address and data buses and provides a 16-bit data bus corresponding to a 16-bit version of the X-bus data portion (XD-bus). External buffers coupled to the XD-bus provide a system data bus (SD-bus) corresponding to the S-bus data portion. The I/O channel is coupled to the SD-bus while system ROM is coupled to the XD-bus. To accommodate the fact that the swapper is internal, the support chip provides independent direction control of the high and low order buffers between the XD-bus and the SD-bus.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: January 18, 1994
    Assignee: Chips and Technologies, Incorporated
    Inventors: Robert M. Pleva, Robert W. Catlin
  • Patent number: 5278945
    Abstract: A neural processor apparatus implements a neural network at a low cost and with high efficiency by simultaneously processing a plurality of neurons using the same synaptic inputs. Weight data is sequentially accessed from an external weight RAM memory to minimize space on the IC. The input data and weight data may be configured as either a single, high-resolution input or a plurality of inputs having a lower resolution, whereby the plurality of inputs are processed simultaneously. A dynamic approximation method is implemented using a minimal amount of circuitry to provide high-resolution transformations in accordance with the transfer function of a given neuron model. The neural processor apparatus may be used to implement an entire neural network, or may be implemented using a plurality of devices, each device implementing a predetermined number of neural layers.
    Type: Grant
    Filed: January 10, 1992
    Date of Patent: January 11, 1994
    Assignee: American Neuralogical, Inc.
    Inventors: Paul M. Basehore, Albert A. Petrick, Jr., David Ratti