Abstract: A method for efficiently utilizing data recording media in a data processing system performing data compression beneath the level of the host processor is disclosed. To improve the ability of a recording media to be copied without increasing host processor overhead, the control unit which sees the compressed data is checked only upon recording a predetermined amount of uncompressed data. At such time, a compression ratio is calculated for the current data set and is used to monitor the recording of the remaining data of the current data set in compressed form. When a predetermined amount of compressed data is estimated to be recorded, the predetermined amount being the minimum storage capacity of a recording media, recording begins on a new recording media.

Abstract: A circuit for transferring data from one bus system to another is disclosed. The circuit allows the write bus to perform write operations indiscriminately of any handshaking, wait states or other control signals which would otherwise reduce the bus efficiency of the system. Similarly, the read bus system has no handshaking or wait states but is provided with a data ready signal to indicate when valid data may be read. This circuit is used in applications where less than 100% data integrity is permissible.

Abstract: A speech coding apparatus and method for use in a speech recognition apparatus and method. The value of at least one feature of an utterance is measured during each of a series of successive time intervals to produce a series of feature vector signals representing the feature values. A plurality of prototype vector signals, each having at least one parameter value and a unique identification value are stored. The closeness of the feature vector signal is compared to the parameter values of the prototype vector signals to obtain prototype match scores for the feature value signal and each prototype vector signal. The identification value of the prototype vector signal having the best prototype match score is output as a coded representation signal of the feature vector signal. Speaker-dependent prototype vector signals are generated from both synthesized training vector signals and measured training vector signals.

Abstract: A voice animation system decomposes pre-recorded samples of actual speech into basic segments to derive speech patterns of a particular speaker to provide parameters and coefficients for use in a text-to-speech synthesizer to artificially synthesize human quality speech with unlimited vocabulary in the voice of the person who provided the pre-recorded samples. The pre-recorded speech samples are further processed to add desired inflection and other auditory effects to create high-quality animated or artificial voices.

Abstract: An adaptive probabilistic neural network (APNN) includes a cluster processor circuit which generates a signal which represents a probability density function estimation value which is used to sort input pulse parameter data signals based upon a probability of obtaining a correct match with a group of input pulse parameter data signals that have already been sorted. In the APNN system, a pulse buffer memory circuit is contained within the cluster processor circuit and temporarily stores the assigned input pulse parameter data signals. The pulse buffer memory circuit is initially empty. As the input pulse parameter data signals are presented to the APNN, the system sorts the incoming data signals based on the probability density function estimation value signal generated by each currently operating cluster processor circuit. The current input pulse parameter data signal is sorted and stored in the pulse buffer memory circuit of the cluster processor circuit.

Abstract: A system and method for striping data to multiple storage devices is provided. One embodiment of the present invention sequentially gates data to a plurality of buffers, wherein only those buffers corresponding to storage devices in use are induced to gate in data. The data is then sent to the storage devices in parallel. Other embodiments further include the use of striping buffers alternatingly used to gate in data, and transfer data to the storage devices.

Abstract: A virtual computer system has a plurality of virtual computers and a virtual computer monitor for monitoring the virtual computers and for providing translation information describing the relationship between a virtual identification of the input/output apparatus structure to be recognized by the virtual computers and a physical identification to be actually used by the input/output apparatus structure. A hardware dynamically creates a subchannel necessary for performing an input/output process of the virtual computers and translation information when the virtual computer monitor provides the translation information to the hardware. The hardware translates the virtual identification to the physical identification based on the translation information when the virtual computer issues the input/output instruction, and for identifying the subchannel, thereby performing the input/output process.

Abstract: A data processing system and method for solving pattern classification problems and function-fitting problems includes a neural network in which N-dimensional input vectors are augmented with at least one element to form an N+j-dimensional projected input vector, whose magnitude is then preferably normalized to lie on the surface of a hypersphere. Weight vectors of at least a lowest intermediate layer of network nodes are preferably also constrained to lie on the N+j-dimensional surface.To train the network, the system compares network output values with known goal vectors, and an error function (which depends on all weights and threshold values of the intermediate and output nodes) is then minimized. In order to decrease the network's learning time even further, the weight vectors for the intermediate nodes are initially preferably set equal to known prototypes for the various classes of input vectors.

Abstract: An apparatus for generating a set of acoustic prototype signals for encoding speech includes a memory for storing a training script model comprising a series of word-segment models. Each word-segment model comprises a series of elementary models. An acoustic measure is provided for measuring the value of at least one feature of an utterance of the training script during each of a series of time intervals to produce a series of feature vector signals representing the feature values of the utterance. An acoustic matcher is provided for estimating at least one path through the training script model which would produce the entire series of measured feature vector signals. From the estimated path, the elementary model in the training script model which would produce each feature vector signal is estimated. The apparatus further comprises a cluster processor for clustering the feature vector signals into a plurality of clusters.

Abstract: An arithmetic and logic processor includes a register file structure wherein each procedure to be processed has assigned thereto a predetermined number of registers referred to as register window. The processor further includes circuitry for comparing a predetermined constant LENGTH with the difference between the register window currently utilized by a procedure under execution and the base address of the register file, and circuitry responsive to the comparing circuitry output to detect when data should be transferred on a window basis to or from the register file from or to a stack memory for saving the register file contents, and circuitry responsive to the decision circuitry output to perform data transfer between the register file and the stack memory. According to such circuitry, overflow and underflow of the register file can be greatly suppressed to improve processing speed of the processor.

Abstract: A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.

Abstract: A method for locking and unlocking a computer address is described. A separate instruction for locking is read. A first value is assigned to a flag to indicate that locking has been requested. An instruction that uses the address is executed. The address is locked such that the address can be accessed by the processor and not by any other processor. A separate instruction for unlocking is read. A second value is assigned to a flag to indicate that unlocking has been requested. A load instruction or a store instruction is executed. The address is unlocked such that the address can be accessed by the processor and by at least one other processor.

Abstract: A bus arbitration system is capable of granting access to an expansion bus to devices following two-wire bus arbitration protocol or a three-wire bus arbitration protocol. The bus arbitration system receives a plurality of bus request signals from a plurality of devices. Each bus request signal is made up of one or more coded pulses and has a predetermined priority. A priority encoder receives the bus request signal and assigns a priority level to each bus request signal. An arbiter determines and stores in memory which bus request signal has a highest priority and whether the device follows two-wire bus arbitration protocol or a three-wire bus arbitration protocol. The expansion bus grants access to the bus to the device having the highest priority once a previous device if any, has relinquished the bus.

Abstract: A neuron unit includes first shift registers for storing first weighting coefficients; second shift registers for storing second weighting coefficients; a first gate circuit for obtaining first logical products of first binary input signals and the first weighting coefficients; a second gate circuit for obtaining second logical products of second binary input signals and the second weighting coefficients; a third gate circuit for obtaining a logical sum of the first logical products, and for outputting a first binary response signal corresponding to the logical sum; a fourth gate circuit for obtaining a logical sum of the second logical products, and for outputting a second binary response signal corresponding to the logical sum; a signal generator for outputting a binary signal; and an output circuit for outputting a binary output signal, the first binary response signal being used as the binary output signal when values of the first and second binary response signals differ from each other, and the binary s

Abstract: The invention relates to the reproduction of high-fidelity multi-dimensional sound fields intended for human hearing. More particularly, the invention relates to the decoding of signals representing such sound fields delivered by one or more delivery channels, but played back over a number of presentation channels which may differ from the number of delivery channels. In a preferred embodiment, a decoder implemented by a discrete digital inverse transform incurs implementation costs roughly proportional to the number of presentation channels.

Abstract: In accordance with the present invention, a neural network comprising an array of neurons (i.e. processing nodes) interconnected by synapses (i.e. weighted transmission links) is utilized to carry out a probabilistic relaxation process. The inventive neural network is especially suited for carrying out a variety of image processing tasks such as thresholding.

Abstract: A speech coding apparatus includes multipliers and prediction filters which successively process a plurality of signal vectors obtained from an index 2.sup.M and dimension N code book to obtain a reproduced speech signal. Error detectors are provided which find the error between the input speech signal and reproduced speech signal. Evaluators are also provided which calculate the optimum signal vectors giving the smallest errors. The multipliers are connected to a reduced code book, which is constituted of n number of code book blocks of index 2.sup.M/n and dimension N/n (where n is an integer of two or more). There are n number of multipliers, n number of prediction filters, n number of error detectors, and n number of evaluators corresponding to the code book blocks.

Abstract: An automatically configurable I/O board and associated software avoids any need for jumpers, switches, or other configuration changes upon installation of the board. Utilization of the main computer capability to select addresses and values likely to be available involves an installation or other routine which arrives at a unique parameter through common commands and repetitive execution. Uniqueness of the parameter or address is accomplished by checking for use elsewhere in the system prior to operation of the board. Steps are taken to avoid any inappropriate changes in conflicting I/O boards by activating components on the board through use of a state machine, by using non-destructive commands for initial checks, by tristating unnecessary lines, and by re-initializing registers whenever a conflict is encountered. Additionally no address space is used to activate the board.

Abstract: The subject of the invention is a learning system for a neural net physically insertable in the learning process, which comprises a detecting member for presenting to said neural net the basic information set that said neural net has to learn in order to provide a desired response; a microprocessor suitable to iteratively execute a learning algorithm based on a comparison among said basic information set itself, the response that the neural net provides and the response that one wants to obtain from the neural net (see FIG. 1).

Abstract: A bus interface employs a bus extender for connecting an auxiliary bus to a single port on a main bus in such a way as to interconnect one or more host computers on the main bus to one or more peripheral devices on the auxiliary bus. The bus extender employs a transceiver coupled to the main bus, another coupled to the auxiliary bus, and signal transfer and logic circuitry passing signals between and controlling the operation of the transceivers. The circuitry also performs all address translation necessary for inter-bus communication. Once communication links have been established with the designated devices on the other bus, the extender sends message data signals received over the one bus directly onto the other bus without modification. Since the interface can comply with SCSI standards, any of a variety of types of commercially available peripheral devices having controllers complying with those standards can be supported on the auxiliary bus.