Abstract: This disclosure includes back pattern counter measures for solid state drives. Embodiments described herein include setting and applying read threshold offsets according to flags set based on an amount of data stored within a memory block (e.g., an “openness” of the block). The flag is implemented during read commands to account for shifts in voltage distribution of open blocks. A value of the flag may be chosen based on a number of word lines included in the block that store data. The read threshold offsets may further be based on at least one of the set flag or an age of a respective NAND cell.

Abstract: Devices and methods for accessing resistive change elements in a resistive change element array to determine resistive states of the resistive change elements are disclosed. According to some aspects of the present disclosure the devices and methods access resistive change elements in a resistive change element array through a variety of operations. According to some aspects of the present disclosure the devices and methods supply an amount of current tailored for a particular operation. According to some aspects of the present disclosure the devices and methods compensate for circuit conditions of a resistive change element array by adjusting an amount of current tailored for a particular operation to compensate for circuit conditions of the resistive change element array.

Abstract: A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.

Abstract: A semiconductor device includes a semiconductor substrate, ground level circuitry, a plurality of stacked memory arrays and a plurality of sense amplifier units. The ground level circuitry is disposed on the semiconductor substrate. The stacked memory arrays are disposed at an elevated level over the ground level circuitry. The sense amplifier units are disposed on the semiconductor substrate and electrically coupled to the stacked memory arrays, wherein at least a portion of each of the sense amplifier units is disposed at the elevated level over the ground level circuitry.

Abstract: A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: Apparatuses, systems, and methods for bias temperature instability (BTI) mitigation. A BTI oscillator provides a periodic BTI signal. A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal. A clock gating circuit passes the clock signal to a clock path when the periodic BTI signal is active. When the memory is in an unclocked mode, where an external clock is not received, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.

Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

Abstract: Memories might include an array of memory cells including a string of series-connected split-gate memory cells, and a controller configured to cause the memory to selectively activate a first memory cell portion of a selected split-gate memory cell of the string of series-connected split-gate memory cells in response to a data state of the first memory cell portion of the selected split-gate memory cell and deactivate a second memory cell portion of the selected split-gate memory cell, and activate a second memory cell portion of each remaining split-gate memory cell of the string of series-connected split-gate memory cells while selectively activating the first memory cell portion of the selected split-gate memory cell and deactivating the second memory cell portion of the selected split-gate memory cell.

Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

Abstract: A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.

Abstract: In accordance with an embodiment, a circuit includes: a trimmable reference current generator having a temperature dependent current output node, the trimmable reference current generator including: a proportional to absolute temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including a first output coupled to the temperature dependent current output node; and a reference interface circuit having an input coupled to the temperature dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.