Patents Examined by Min Huang
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Patent number: 11705165Abstract: Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.Type: GrantFiled: October 26, 2021Date of Patent: July 18, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Shu-Liang Ning, Jun He, Zhan Ying, Jie Liu
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Patent number: 11705188Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.Type: GrantFiled: November 17, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Toshiaki Tsukihashi, Kenichi Watanabe, Kazuyuki Morishige, Moeha Shibuya, Kumiko Ishii
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Patent number: 11705185Abstract: Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.Type: GrantFiled: June 29, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventor: Daniele Vimercati
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Patent number: 11699693Abstract: A memory device includes first and second chips. The first chip includes a memory cell array disposed on a first substrate, and first metal pads on a first uppermost metal layer of the first chip. The second chip includes peripheral circuits disposed on a second substrate, and second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array. A first metal pad and a second metal pad are connected in a first area, the first metal pads being connected to the memory cell array and the second metal pad being connected to the peripheral circuits. A further first metal pad and a further second metal pad are connected in a second area, the further first metal pad being not connected to the memory cell array and the further second metal pad being connected to the peripheral circuits.Type: GrantFiled: December 8, 2021Date of Patent: July 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jooyong Park, Chanho Kim, Daeseok Byeon
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Patent number: 11699479Abstract: A nonvolatile memory apparatus may include a control circuit, a sense amplifier, and a reference generator. The control circuit may apply a read voltage across a target memory cell through a selected global bit line and a selected global word line. The sense amplifier may generate an output signal by comparing voltage levels of the selected global word line and a reference line. The reference generator may change the voltage level of the reference line by charging and discharging a capacitor that is coupled to the reference line.Type: GrantFiled: June 21, 2021Date of Patent: July 11, 2023Assignee: SK hynix Inc.Inventor: Moo Hui Park
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Patent number: 11694742Abstract: An apparatus is described. The apparatus according to an embodiment includes a voltage dividing resistor circuit formed on a semiconductor substrate and including first and second resistors and first and second selector switches. The first and second resistors and the first and second selector switches are arranged with one of first and second layouts. The first layout is such that the first and second selector switches are placed between the first and second resistors. The second layout is such that the first and second resistors are placed between the first and second selector switches.Type: GrantFiled: September 11, 2020Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Takayori Hamada, Yuki Miura, Hiroshi Shimizu
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Patent number: 11696454Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.Type: GrantFiled: May 3, 2021Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
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Patent number: 11688486Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.Type: GrantFiled: August 16, 2021Date of Patent: June 27, 2023Assignee: Apple Inc.Inventors: Shahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
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Patent number: 11688437Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.Type: GrantFiled: September 22, 2021Date of Patent: June 27, 2023Assignee: Apple Inc.Inventors: Michael A. Dreesen, Shawn Searles, Jaemyung Lim, Jacek R. Wiatrowski
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Patent number: 11682462Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.Type: GrantFiled: July 30, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Jung Sheng Hoei
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Patent number: 11676636Abstract: Implementations described and claimed herein provide a high-capacity, high-bandwidth scalable storage device. The scalable storage device includes a layer stack including at least one memory layer and at least one optical control layer positioned adjacent to the memory layer. The memory layer includes a plurality of memory cells and the optical control layer is adapted to receive optically-encoded read/write signals and to effect read and write operations to the plurality of memory cells through an electrical interface.Type: GrantFiled: August 31, 2020Date of Patent: June 13, 2023Assignee: SEAGATE TECHNOLOGY LLCInventors: Kevin A. Gomez, Dan Mohr, Daniel Joseph Klemme, Aditya Jain
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Patent number: 11676649Abstract: Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).Type: GrantFiled: July 22, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventor: Makoto Kitagawa
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Patent number: 11676681Abstract: A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.Type: GrantFiled: July 22, 2021Date of Patent: June 13, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi
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Patent number: 11670363Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.Type: GrantFiled: April 23, 2021Date of Patent: June 6, 2023Assignee: Arm LimitedInventors: Rahul Mathur, Mudit Bhargava, Andy Wangkun Chen
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Patent number: 11670361Abstract: An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.Type: GrantFiled: July 15, 2021Date of Patent: June 6, 2023Assignee: Synopsys, Inc.Inventors: Moon-Hae Son, Niranjan Behera
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Patent number: 11669278Abstract: Methods, systems, and devices related to page policies for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may be configured to receive a read command for data stored in the memory array and transfer the data from the memory array to the signal development cache. The memory device may be configured to sense the data using an array of sense amplifiers. The memory device may be configured to write the data from the signal development cache back to the memory array based on one or more policies.Type: GrantFiled: December 20, 2019Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Dmitri A. Yudanov, Shanky Kumar Jain
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Patent number: 11651816Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: GrantFiled: July 22, 2021Date of Patent: May 16, 2023Assignee: SURECORE LIMITEDInventors: Stefan Cosemans, Bram Rooseleer
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Patent number: 11636905Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block having memory cells connected to word lines and arranged in strings and is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The apparatus has a temperature measuring circuit configured to detect an ambient temperature of the apparatus. A control circuit is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit applies an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing in the erase operation.Type: GrantFiled: December 7, 2020Date of Patent: April 25, 2023Assignee: SanDisk Technologies LLCInventors: Sarath Puthenthermadam, Huai-yuan Tseng
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Patent number: 11636886Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.Type: GrantFiled: August 3, 2021Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Aaron S. Yip, Theodore T. Pekny
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Patent number: 11636894Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.Type: GrantFiled: June 1, 2021Date of Patent: April 25, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Heekyung Choi, Taemin Choi, Seongook Jung, Keonhee Cho