Patents Examined by Min Huang
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Patent number: 11531471Abstract: A memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array are independent. The first memory array includes a plurality of general bits and the second memory array includes a plurality of spare bits. An address of defective bit in the first memory array is stored in the second memory array, and the memory circuit repairs the defective bit by one of the spare bits according to the address.Type: GrantFiled: April 9, 2021Date of Patent: December 20, 2022Assignee: NS Poles Technology Corp.Inventor: Chuang Lung Chiu
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Patent number: 11521672Abstract: A semiconductor device includes: a multi-level receiver including N sense amplifiers and a decoder decoding an output of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number, higher than 2, and where N is a natural number, lower than M); a clock buffer receiving a reference clock signal; and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and individually determining a phase of each of the N clock signals using the output of the N sense amplifiers.Type: GrantFiled: April 14, 2021Date of Patent: December 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeokjun Choi, Jindo Byun, Younghoon Son, Youngdon Choi, Junghwan Choi
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Patent number: 11514995Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.Type: GrantFiled: March 24, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Nathan A. Eckel, Keith A. Benjamin
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Patent number: 11514986Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: GrantFiled: March 16, 2021Date of Patent: November 29, 2022Assignee: Kioxia CorporationInventors: Kengo Kurose, Masanobu Shirakawa, Hideki Yamada, Marie Takada
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Patent number: 11508455Abstract: Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.Type: GrantFiled: June 9, 2021Date of Patent: November 22, 2022Assignee: Micron Technology, Inc.Inventor: Ferdinando Bedeschi
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Patent number: 11495638Abstract: Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.Type: GrantFiled: August 25, 2019Date of Patent: November 8, 2022Assignee: TETRAMEM INC.Inventors: Wenbo Yin, Ning Ge
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Patent number: 11495306Abstract: An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.Type: GrantFiled: February 15, 2021Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventors: Michele Piccardi, Xiaojiang Guo, Kalyan Chakravarthy C. Kavalipurapu
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Patent number: 11487476Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to receive a first command set, receive a second command set related to a read operation while rejecting a command set related to a write operation or erase operation in response to the first command set, and execute the read operation on the memory cell array in response to the second command set.Type: GrantFiled: February 25, 2021Date of Patent: November 1, 2022Assignee: KIOXIA CORPORATIONInventor: Yoshikazu Harada
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Patent number: 11481299Abstract: A system includes a memory device with microbumps and a processing device. The processing device is operatively coupled with the memory device to perform operations. The operations include transmitting data for a machine learning operation based on a set of the microbumps of the memory device where the data is being stored at the memory device. In addition, the operations include determining a change in a condition of the machine learning operation. Furthermore, the operations include that, in response to determining the change in the condition of the machine learning operation, determining a new set of the microbumps of the memory device that are to transmit subsequent data for the machine learning operation. Moreover, the operations include transmitting the subsequent data using the new set of microbumps of the memory device.Type: GrantFiled: December 4, 2019Date of Patent: October 25, 2022Assignee: MICRON TECHNOLOGY, INC.Inventor: Poorna Kale
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Patent number: 11462263Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A column multiplexer selects from a plurality of columns using a pair of pass transistor for each column. The column multiplexer drives a true input node and a complement input node of an output data latch.Type: GrantFiled: December 22, 2020Date of Patent: October 4, 2022Assignee: QUALCOMM IncorporatedInventors: Changho Jung, Arun Babu Pallerla, Chulmin Jung
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Patent number: 11456030Abstract: A static random access memory SRAM unit and a related apparatus are provided, to reduce power consumption of an SRAM when the SRAM memory is accessed. The SRAM unit is located in an SRAM memory, and the SRAM memory includes an SRAM storage array including a plurality of SRAM units. The SRAM unit includes: a storage circuit, connected to each of a write circuit and a read circuit, and configured to store data; the write circuit, configured to write data into the storage circuit; and the read circuit, configured to: after a read enabling signal is valid, enable data on a read bit line connected to the SRAM unit to be the data stored in the storage circuit.Type: GrantFiled: February 26, 2021Date of Patent: September 27, 2022Assignees: Huawei Technologies Co., Ltd., Tsinghua UniversityInventors: Han Xu, Fei Qiao, Miao Zheng
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Patent number: 11450401Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to determining that the CSP is solvable and has a solution satisfying the constraints, the at least one fail bit is repaired using the available repair resource in accordance with the solution of the CSP.Type: GrantFiled: December 1, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Katherine H. Chiang, Chien-Hao Huang, Cheng-Yi Wu, Chung-Te Lin
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Patent number: 11450391Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.Type: GrantFiled: September 15, 2020Date of Patent: September 20, 2022Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo
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Patent number: 11450672Abstract: An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.Type: GrantFiled: April 27, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Charles Augustine, Somnath Paul, Muhammad M. Khellah, Chen Koren
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Patent number: 11450383Abstract: A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line.Type: GrantFiled: February 24, 2021Date of Patent: September 20, 2022Assignee: KIOXIA CORPORATIONInventors: Hiroki Date, Takeshi Nakano
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Patent number: 11443795Abstract: A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.Type: GrantFiled: July 12, 2017Date of Patent: September 13, 2022Assignee: Ambiq Micro, Inc.Inventor: Christophe J. Chevallier
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Patent number: 11443782Abstract: An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.Type: GrantFiled: May 3, 2021Date of Patent: September 13, 2022Assignee: SK hynix Inc.Inventor: Woongrae Kim
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Patent number: 11430511Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.Type: GrantFiled: December 10, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventor: Hernan A. Castro
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Patent number: 11430493Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.Type: GrantFiled: March 17, 2021Date of Patent: August 30, 2022Assignee: QUALCOMM INCORPORATEDInventors: Seyed Arash Mirhaj, Ankit Srivastava, Sameer Wadhwa, Ren Li, Suren Mohan
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Patent number: 11430501Abstract: According to one embodiment, a memory system is disclosed. The system includes a nonvolatile memory, a controller which controls the nonvolatile memory and to which a first voltage is supplied, and a circuit to which first and second signals from a host device are input, or the first signal is not input and the second signal is input from the host device, when the memory system is connected to the host device. The circuit converts a second voltage of the second signal into the first voltage when the first and second signal have the second voltage and the second voltage is lower than the first voltage, and does not convert a voltage of the second signal into the first voltage when the first signal is not input and the voltage of the second signal is the first voltage.Type: GrantFiled: March 18, 2021Date of Patent: August 30, 2022Assignee: Kioxia CorporationInventor: Hajime Matsumoto
