Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

Abstract: Systems, apparatuses, and methods for efficiently performing operations system are disclosed. A computing system uses a memory for storing data, and one or more processing units. The memory includes multiple rows for storing the data with each intersection of a row and a column being a memory bit cell. The memory processes operations. For particular operations, the two or more operands are accessed simultaneously for generating a result without being read out and stored. Two indications are generated specifying at least a first row and a second row targeted by the operation. The memory generates a result by performing the operation for each of the one or more cells in the first row a stored value with a respective stored value in the one or more cells in the second row.

Abstract: A memory device includes a memory cell chip, a peripheral circuit chip, and a routing wire. The memory cell chip includes a memory cell array disposed on a first substrate, and a first metal pad on a first uppermost metal layer. The peripheral circuit chip includes circuit devices disposed on a second substrate, and a second metal pad on a second uppermost metal layer of the peripheral circuit chip. The memory cell chip and the peripheral circuit chip are vertically connected to each other by the first metal pad and the second metal pad in a bonding area. The routing wire is electrically connected to the peripheral circuit and is disposed in the first uppermost metal layer or the second uppermost metal layer and is disposed in a non-bonding area in which the memory cell chip and the peripheral circuit chip are not electrically connected to each other.

Abstract: An electronic device includes a first input that receives an input signal when the electronic device is in operation, a long L gate comprising a long L transistor, a first activation transistor coupled to a gate of the long L transistor, and a second activation transistor coupled to the gate of the long L transistor. The electronic device also includes a switch directly coupled to a second input of the long L gate, a path directly coupled to a first output of the long L gate, a capacitor coupled to the path, and a second output that when in operation transmits an output signal as a delayed signal with respect to the input signal.

Abstract: A magnetoresistive random access memory (MRAM) includes a plurality of input/output units. Each input/output units can read and write memory cells simultaneously. So a read/write column to column delay time (tCCD) of the MRAM is equal to or shorter than a read/write column to column delay time of a dynamic random access memory (DRAM). Consequently, a data-rate of the MRAM is equal to or shorter than a data-rate of the DRAM.

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a string having a plurality of memory cells in which data is stored, and a page buffer coupled to the string through a bit line and configured to precharge the bit line, or sense voltage or current of the bit line. The page buffer may include a first switch configured to transfer the voltage of the bit line to a common sensing node in response to a page buffer sensing signal, a second switch configured to transfer a supply voltage to the common sensing node in response to a common sensing signal, and a third switch configured to couple the common sensing node to a latch in response to a sensing signal and adjust voltage of the common sensing node depending on a voltage level of the sensing signal.

Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

Abstract: A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a bit line, a first word line, a source line, and a memory cell. The memory cell includes a first switch transistor and a magnetic tunnel junction. A first side of the magnetic tunnel junction is connected to a first terminal of the first switch transistor. The bit line is connected to a second terminal of the first switch transistor. The source line is connected to a second side of the magnetic tunnel junction. The first word line is connected to a third terminal of the first switch transistor.

Abstract: A method for controlling a temperature in an air conditioning device according to an embodiment of the present invention includes: calculating an exponentially-weighted running mean temperature for outdoor temperatures measured for a predetermined period, setting a variable constant and a fixed constant according to the exponentially-weighted running mean temperature and an operation condition, setting a comfort temperature by multiplying the exponentially-weighted running mean temperature by the variable constant and adding the fixed constant, and controlling an indoor temperature by using the set comfort temperature.

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

Abstract: A method of producing a multilayer magnetoelectronic device and a related device. The method includes depositing a multilayer structure including at least two ferromagnetic layers disposed one on top of the other and each having a magnetic anisotropy with a corresponding magnetic moment. A magnetization curve is specified for the magnetoelectronic device. The number of ferromagnetic layers and, for each of the ferromagnetic layers, the magnetic moment and the magnetic hardness for obtaining the specified magnetization curve are determined. For each of the ferromagnetic layers a magnetic material, a thickness, an azimuthal angle and an angle of incidence are determined for obtaining the determined magnetic moment and magnetic hardness of the respective ferromagnetic layer. The multilayer structure is deposited using the determined material, thickness, azimuthal angle and angle of incidence for each of the ferromagnetic layers.

Abstract: In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.

Abstract: Methods of operating a memory device are disclosed. A method may include receiving, at a first die of a number of dies, a first number of bits including one or more command bits, one or more identification bits, and a first number of address bits associated with a command during a first clock cycle. The method may further include conveying, from the first die to at least one other die, at least some of the first number of bits. Further, the method may include receiving, at the first die, a second number of bits including a second number of address bits associated with the command during a second, subsequent clock cycle. Also, the method may include conveying, from the first die to the at least one other die, at least some of the second number of bits. Memory devices and electronic systems are also disclosed.

Abstract: A non-volatile memory and a data writing method are provided. The non-volatile memory includes a memory array and a memory controller. The memory array has a plurality of memory cells. The memory controller is configured to perform a data write operation on a plurality of selected memory cells. In the data write operation, the memory controller records a total number of times that a data write pulse is supplied, compares the total number of times of the data write pulse to a preset threshold value to obtain an indication value, and adjusts an absolute value of a voltage of the data write pulse according to the indication value.

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

Abstract: One embodiment provides an apparatus. The apparatus may include memory circuitry to store tensor data representing a tensor. The apparatus may include memory controller circuitry to access the memory circuitry. The apparatus may include processor circuitry to: receive a request for a tensor operation; generate a plurality of sub-commands for the tensor operation; and provide the sub-commands to memory controller circuitry to perform the tensor operation based on instructions contained in one or more of the sub-commands. The instructions contained in one or more of the sub-commands may include identify addresses in memory to access; activate one or more rows in the memory circuitry that correspond to the addresses; and transfer tensor data to and/or from the memory circuitry.