Abstract: This disclosure describes, in part, techniques for provisioning components. For instance, a component may be initially provisioned by a first system. To initially provision the component, the component may receive first data representing a uniform device type, a device identifier, a serial number, and/or a first certificate chain. The component may then store the first data in memory. Additionally, the component may be provisioned using a second system. To provision the component, the component may receive second data representing a product device type, a code, and a second certification chain. The second data received during the second provisioning may be associated with one more capabilities of a device. The component may then store the second data in the memory.

Abstract: A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.

Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

Abstract: A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.

Abstract: Discussed herein are devices, systems, and methods for secure access to offline data. A method can include configuring a device in a task retrieval state and retrieving a task to be executed on a cold storage device while the device is in the task retrieval state, configuring the device in a disconnected state after retrieving the task, and configuring the device in a task execution state after the device is in the disconnected state and executing the task on the cold storage while the device is in the task execution state. In the task retrieval state, the device can communicate with a buffer network and cannot communicate with a cold network. In the disconnected state, the device cannot communicate with either the cold network or the buffer network. In the task execution state, the device can communicate with the cold network and cannot communicate with the buffer network.

Abstract: A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.

Abstract: A memory device and a method of operating the same are provided. The memory device may include a peripheral circuit configured to perform a plurality of program loops and program a page selected from among the plurality of pages, wherein the peripheral circuit may count a number of memory cells whose threshold voltages have increased up to a first target voltage, among a part of memory cells included in the selected page, and may perform a current sensing check operation of determining whether a verify operation performed in a previous program loop has passed or failed, and a control logic circuit configured to control the peripheral circuit so that the current sensing check operation is performed when the number of memory cells whose threshold voltages have increased up to the first target voltage, is equal to or greater than a reference number of memory cells.

Abstract: Methods, non-transitory computer readable media, and query verification apparatuses are disclosed that receive data, store the data into a table of a database, and receive a query that is associated with the database table. A query plan and a query result are generated for the query, one or more partial proofs are generated from one or more commitments, and an overall proof is generated from the one or more partial proofs. Each of the one or more partial proofs is associated with at least one node of the query plan in some examples, which can include a directed acyclic graph. The overall proof is returned along with the query result in response to the query to facilitate verification of the query result. One or more GPUs are configured to generate the one or more commitments in some examples to thereby accelerate the verification process and improve database scalability.

Abstract: The present technology includes memory device and a method of operating the same. The memory device includes a memory block including a plurality of pages, a voltage generator configured to generate a program voltage or a verify voltage applied to a selected page among the plurality of pages, a page buffer connected to the selected page through bit lines and configured to perform a precharge operation, an evaluation operation, and a sensing operation on the bit lines during a verify operation, and a control circuit configured to store page addresses of slow pages of which a program operation speed for each is slower than an average program speed of the plurality of pages, and adjust an evaluation time of the evaluation operation according to the page addresses.

Abstract: Examples associated with cryptographic key security are described. One example system includes a secure storage accessible to a basic input/output system (BIOS). A BIOS security module stores an authorization value in a fixed location in the secure storage. The authorization value is stored by the BIOS during a boot of the system. A cryptographic key module reads the authorization value from the fixed location, overwrites the authorization value in the fixed location, and obtains a cryptographic key using the authorization value.

Abstract: A method includes detecting proximity between a mobile device and a remote device associated with a transaction reserved by a user of the mobile device and a mode of the electronic device. A verification password is sent to the remote device responsive to detecting the proximity and the mode. A device includes a module to detect proximity between the device and a remote device associated with a transaction reserved by a user of the device occurring within a predefined distance threshold and a processor coupled to the module. A device includes another module to detect a stationary mode of the electronic device occurring for at least a predefined duration threshold. The processor is sends a verification password to the remote device responsive to detecting the proximity and the mode.

Abstract: Embodiments discussed herein may be generally directed to systems and techniques to generate a quality score based on an observation and an action caused by an actor agent during a testing phase. Embodiments also include determining a temporal difference between the quality score and a previous quality score based on a previous observation and a previous action, determining whether the temporal difference exceeds a threshold value, and generating an attack indication in response to determining the temporal difference exceeds the threshold value.

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Abstract: Some examples relate generally to computer architecture software for data classification and information security and, in some more particular aspects, to verifying audit events in a file system.

Abstract: The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various embodiments. Historically, DDIO has enabled performance advantages that have outweighed its security risks. DDIO circuitry may be configured to secure DDIO data by using encryption circuitry that is manufactured for use in communications with main memory along the direct memory access (DMA) path. DDIO circuitry may be configured to secure DDIO data by using DDIO encryption circuitry manufactured for use by or manufactured within the DDIO circuitry. Enabling encryption and decryption in the DDIO path by the DDIO circuitry has the potential to close a security gap in modern data central processor units (CPUs).

Abstract: The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

Abstract: A method may include allocating a number of public keys, where each respective public key is allocated to a respective entity of a number of entities; storing a number of private keys, where each respective private corresponds to a respective public key; storing one or more decryption algorithms, where each respective decryption algorithm is configured to decrypt data previously encrypted using at least one encryption algorithm of the encryption algorithms. Each respective encryption algorithm may be configured to encrypt data using at least one public key. Each respective decryption algorithm may be configured to decrypt data using at least one private key. The method may include receiving encrypted data, where the encrypted data is encrypted using a first public key and a first encryption algorithm, and the encrypted data is provided over a network.

Abstract: An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.

Abstract: Systems and methods for detecting a rogue network device at a physical layer include obtaining physical layer characteristics of a link between a first network device and a second network device; analyzing the physical layer characteristics of the link; and detecting the rogue network device based on the analyzed physical layer characteristics, wherein the rogue network device was inserted in the link and causes detectable variances in the physical layer characteristics. The physical layer characteristics can include one of noise introduced in clock frequency and jitter.