Abstract: Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a dual interlock storage cell (DICE) latch circuit including a first input node corresponding to a first path and a second input node corresponding to a second path. The first input node is electrically isolated from the second input node.

Abstract: The present invention provides a method of integrating existing strong encryption methods into the processing of a .ZIP file to provide a highly secure data container which provides flexibility in the use of symmetric and asymmetric encryption technology. The present invention adapts the well-established .ZIP file format to support higher levels of security and multiple methods of data encryption and key management, thereby producing a highly secure and flexible digital container for electronically storing and transferring confidential data.

Abstract: A communication device. The communication device comprises a central processing unit (CPU), a graphics processing unit (GPU), and a non-transitory memory comprising executable instructions for a sharing application that when executed by at least one of the CPU or the GPU, causes the sharing application to transmit an executable of a trusted application to an endpoint communication device, begin execution of the sharing application in a trusted security execution zone (TSZ) execution mode for sharing media content, instantiate a trustlet application that begins execution by the CPU or the GPU in the TSZ execution mode, display a unit of media content on the communication device, determine whether the unit of media content comprises confidential information, and in response to a determination the unit of media content comprises confidential information, transmit commands to the trusted application to control one or more functions at the endpoint communication device.

Abstract: A method of interpreting an authorization token is described herein. The service can receive an authorization token from a client device, and validate a signature of the authorization token. The service can identify an allowed function value associated at least part of an entitlement representation contained in a body of the authorization token. The service can convert the allowed function value to an allowed function bitmask that includes bits at a plurality of bit positions that are set to values indicating whether the subscriber element has attributes associated with each of the plurality of bit positions on a predefined attribute list. The service can determine whether the allowed function bitmask indicates that the subscriber element has one or more qualifying attributes that entitle a user of the client device to access the service.

Abstract: A non-transitory computer-readable storage medium storing a program that cause a processor included in an information processing apparatus to execute a process, the process includes collecting a plurality of types of cyberattack information; evaluating a number of types of cyberattacks in which feature information of the cyberattack appears based on the collected cyberattack information; and when receiving specification of the feature information of a cyberattack, responding evaluation results of the number of types of cyberattacks in which the specified feature information of the cyberattack appears.

Abstract: A sending device may send data intended for a target device. An intermediate device may intercept the data sent from the sending device and forward the communications to the target device. Security data (e.g., a security certificate for authentication) along with an encrypted version of the security data may be sent at the application layer such that it passes from the sending device, through the intermediate device, and to the target device without being analyzed or modified by the intermediate device. The target device may use the encrypted security data and the security data to verify the identity of the sending device.

Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

Abstract: A semiconductor memory with temperature dependence is provided. The semiconductor memory includes a memory array, a temperature sensor circuit and a pump circuit. The temperature sensor circuit is configured to provide a temperature dependent signal. The pump circuit is coupled to the temperature sensor circuit and the memory array. The pump circuit is configured to output a charge-pump output voltage to the memory array according to the temperature dependent signal. The charge-pump output voltage depends on the temperature dependent signal.

Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.

Abstract: A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: A memory device includes a level down shifting driver circuit. The level down shifting driver circuit include input circuitry having at least one input port, and a cross-junction circuitry electrically coupled to the input circuitry and configured to receive a first signal from the input circuitry to drive one or more devices included in the cross-junction circuitry. The level down shifting driver circuit further includes an output drive circuitry electrically coupled to the cross-junction circuitry and configured to receive a second signal from the cross-junction circuitry, wherein the output drive circuitry comprises an output line configured to deliver a first voltage output based on a first input voltage received by the input circuitry, and a second voltage output based on a second input voltage received by the input circuitry.

Abstract: A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.

Abstract: In some examples, a memory device may perform refresh operations responsive to internal and/or external commands. internal refresh commands may include auto-refresh commands and row hammer (e.g., targeted) refresh commands. External commands may include refresh management commands. In some examples, the external command may cause a refresh operation to occur after a number of activation commands. The memory device may monitor row addresses associated with the activation commands. In some examples, the memory device may skip a refresh operation indicated by a refresh management command if none of the row addresses associated with the activation commands occurs at a high frequency. In some examples, row addresses may be determined to be aggressor row addresses if a received row address matches a previously received row address.

Abstract: Systems and techniques described herein are concerned with providing supervisory control of computer programs. In particular, a method for executing application code defining a computer program includes providing a “kill switch” to the operator, which allows the operator to disable the computer program. The kill switch is configured so that the computer program is incapable of over-riding it.

Abstract: Non-volatile memory structures are presented for a content addressable memory (CAM) that can perform in-memory search operations for both ternary and binary valued key values. Each ternary or binary valued key bit is stored in a pair of memory cells along a bit line of a NAND memory array, with the stored keys searched by applying each ternary or binary valued bit of an input key as voltage levels on a pair of word lines. The system is highly scalable. The system can also be used to perform nearest neighbor searches between stored vectors and an input vector to find stored vectors withing a specified Hamming distance of the input vector.

Abstract: An electronic device and an operating method thereof according to various example embodiments may be configured to acquire video data and audio data, to scramble audio data of a time interval (?T) in non-time order, and to store the video data and the scrambled audio data together. According to an example embodiment, the time interval (?T) may be fixed to be the same with respect to continuous audio data. According to another example embodiment, the time interval (?T) may vary using a function of receiving an input of a secret key and order and outputting a unique value, such as a Hash-based Message Authentication Codes (HMAC)-based One-time Password (HOTP) algorithm.

Abstract: Methods and systems for implementing DevID enrollment for hardware redundant Trust Platform Modules (TPMs), are described. A system can include hardware redundancy for management modules, and for TPMs that correspond to each management module. Accordingly, a product can have a dual-TPM configuration, where both modules are associated with the same product. Further, a process that particularly considers the presence of dual-TPMs for creating, issuing, and enrolling DevID certificates is described. The process issues and maintains DevID certificates for each TPM by synchronizing dual sessions that correspond to each TPM. Also, the process accounts for duplicate identification data, for example allowing the certificate authority (CA) to sign certificates for dual-TPMs linked to the same chassis number. The process can include performing validation checks, rendezvous points, and locks to ensure that DevID certificates are successfully issued for each of the dual-TPMs, respectively.

Abstract: A first current bin boundary for a first voltage bin on a first target die of a set of dies at a memory device is identified by accessing a block family metadata table including an entry for each block family of a memory device. The first current bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family corresponding to a first new bin boundary for the first voltage bin is determined. The first bin boundary is determined based on a calibration scan performed for the first voltage bin. A first new bin boundary for the first voltage bin is determined on each die of the set of dies based on the first bin boundary offset.

Abstract: Described are techniques for privacy-preserving endorsements in blockchain transactions. The techniques include a method comprising associating a ledger key in a local collection with an ephemeral key, where the ephemeral key is a re-randomization of a key associated with a first organization. The method further comprises generating, by a first peer associated with the first organization, an anonymous endorsement of a transaction in a blockchain using the ephemeral key. The method further comprises determining, by a second peer associated with the first organization, that the first peer endorsed the transaction. The method further comprises retrieving, by the second peer, a preimage from the first peer. The method further comprises providing information including the anonymous endorsement and the transaction to a second organization associated with the blockchain, where the anonymous endorsement is anonymous to peers associated with the second organization.