Abstract: A package structure and its manufacturing method are provided. The package structure includes a substrate with a recess, and a first MEMS chip, a first intermediate chip, a second MEMS chip and a first capping plate sequentially formed on the substrate. The lower surface of the first MEMS chip has a first sensor or a microactuator. The upper surface of the second MEMS chip has a second sensor or a microactuator. The first intermediate chip has a through-substrate via, and includes a signal conversion unit, a logic operation unit, a control unit, or a combination thereof. The package structure includes at least one of the first sensor and the second sensor.

Abstract: A method for preparing a flexible electrode is provided. The method comprises sequentially forming a flexible base layer and an intermediate conductive layer on a carrier plate; treating an elastomeric template having an electrode pattern with an acid, followed by transferring and printing the electrode pattern onto the intermediate conductive layer to form an electrode inducing layer; forming a titanium dioxide-polydopamine composite layer in a gap of the electrode inducing layer; forming a platinum electrode layer on the titanium dioxide-polydopamine composite layer; removing the carrier plate. The invention solves the problems of slow formation of a polydopamine film and slow formation of a platinum electrode layer. A flexible electrode is further provided.

Abstract: Methods of forming a microelectromechanical device are disclosed. In some embodiments, a first layer is deposited on a backplane having at least two electrodes. One or more electrical contacts over the first layer are formed. Forming the one or more electrical contacts includes: depositing a first ruthenium layer over the first layer, depositing a titanium nitride layer over the first ruthenium layer, depositing a second ruthenium layer over the titanium nitride layer, etching the second ruthenium layer with a first etchant, etching the titanium nitride layer with a second etchant different than the first etchant; and etching the first ruthenium layer with the first etchant. Additionally, a beam is formed above one or more electrical contacts, the beam being spaced from the one or more electrical contacts and a top electrode is formed above the beam. A seal layer above the beam to enclose the beam in a cavity.

Abstract: A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Abstract: An optical device includes a support portion a movable unit and a pair of torsion bars disposed on both sides of the movable unit on a first axis. The movable unit includes a main body portion, a ring-shaped portion surrounding the main body portion when viewed from a predetermined direction perpendicular to the first axis, two connection portions connecting the main body portion and the ring-shaped portion to each other, and a rib portion provided to the main body portion. Each of the two connection portions includes two connection regions that are separated from each other by a space and the each of the two connection region connects the main body portion and the ring-shaped portion to each other. The rib portion includes four extending portions radially extending between a center of the main body portion and the four connection regions respectively when viewed from the predetermined direction.

Abstract: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.

Abstract: A MEMS device is provided. The MEMS device includes a substrate having at least one contact, a first dielectric layer disposed on the substrate, at least one metal layer disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the metal layer and having a recess structure, and a structure layer disposed on the second dielectric layer and having an opening. The opening is disposed on and corresponds to the recess structure, and the cross-sectional area at the bottom of the opening is smaller than the cross-sectional area at the top of the recess structure. The MEMS device also includes a sealing layer, and at least a portion of the sealing layer is disposed in the opening and the recess structure. The second dielectric layer, the structure layer, and the sealing layer define a chamber.

Abstract: A microelectromechanical structure, including a functional element situated in a cavity of the microelectromechanical structure. The functional element includes an aluminum nitride layer. The cavity is closed by a cap layer. The cap layer includes epitaxial silicon. A method for manufacturing a micromechanical structure is also described.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

Abstract: An apparatus includes a biosensor integrated circuit (IC) chip with sensing zones and/or well structures configured to receive a liquid with biological analytes. The chip includes passivation and etch stop layers with an opening over a channel layer and an array of liquid gated field effect transistors with a 2D channel disposed on a dielectric oxide layer. A conductive drain and a conductive source form edge and/or top side contacts with opposite ends of the 2D channel. The chip further includes reference electrodes formed in a metal layer, configured to contact the liquid, and disposed at a horizontal distance apart from the graphene channels. The transistors are operable to enable a set of measurements to sense parameters of the biological analytes based on changes in a shape of Id-Vgs transconductance curves. A system and a method have similar structures and perform the functions of the apparatus.

Abstract: The magnetoresistive stack or structure of a magnetoresistive device includes one or more electrodes or electrically conductive lines, a magnetically fixed region, a magnetically free region disposed between the electrodes or electrically conductive lines, and a dielectric layer disposed between the free and fixed regions. The magnetoresistive device may further include a spin-Hall (SH) material proximate to at least a portion of the free region, and one or more insertion layers comprising antiferromagnetic material.

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Abstract: A method for manufacturing an optical device includes: preparing a semiconductor substrate that includes a portion corresponding to a base, a movable unit, and an elastic support portion; forming a first resist layer in a region corresponding to the base on a surface of a first semiconductor layer which is opposite to an insulating layer; forming a depression in the first semiconductor layer by etching the first semiconductor layer using the first resist layer as a mask; forming a second resist layer in a region corresponding to a rib portion on a bottom surface of the depression, a side surface of the depression, and the surface of the first semiconductor layer which is opposite to the insulating layer; and forming the rib portion by etching the first semiconductor layer until reaching the insulating layer using the second resist layer as a mask.

Abstract: A micro-nano channel structure, a method for manufacturing the micro-nano channel structure, a sensor, a method for manufacturing the sensor, and a microfluidic device are provided by the embodiments of the present disclosure. The micro-nano channel structure includes: a base substrate; a base layer, on the base substrate and including a plurality of protrusions; and a channel wall layer, on a side of the plurality of the protrusions away from the base substrate, and the channel wall layer has a micro-nano channel; a recessed portion is provided between adjacent protrusions of the plurality of the protrusions, and an orthographic projection of the micro-nano channel on the base substrate is located within an orthographic projection of the recessed portion on the base substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: A thin film transistor (TFT) substrate comprises a TFT located on a substrate and including a gate electrode, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer, the gate electrode and the second semiconductor layer vertically stacked, and the first and second semiconductor layers are made of polycrystalline silicon, and wherein the first and second semiconductor layers are electrically connected to each other in series and respectively include first and second channel portions, and at least one of the first and second channel portions has a bent structure in a plan view.

Abstract: A memory device including a rectangular shaped via for at least one Vss node connection. In some embodiments, the rectangular shaped via has a length/width of greater than 1.5. The rectangular shaped via may be disposed on the Via0 and/or Via1 layer interfacing a first metal layer (e.g., M1). The memory cell may also include circular/square shaped vias having a length/width of between approximately 0.8 and 1.2. The circular/square shaped vias may be coplanar with the rectangular shaped vias.