Abstract: A method for providing a semiconductor layer arrangement on a substrate which comprises providing a semiconductor layer arrangement having a functional layer and a semiconductor substrate layer, attaching the semiconductor layer arrangement to a glass substrate layer such that the functional layer is arranged between the glass substrate layer and the semiconductor substrate layer, and removing the semiconductor substrate layer at least partially such that the glass substrate layer substitutes the semiconductor substrate layer as the substrate of the semiconductor layer arrangement.

Abstract: A microelectromechanical device comprising a mobile rotor in a silicon wafer. The rotor comprises one or more high-density regions. The one or more high-density regions in the rotor comprise at least one high-density material which has a higher density than silicon. The one or more high-density regions have been formed in the silicon wafer by filling one or more fill trenches in the rotor with the at least one high-density material. The one or more fill trenches have a depth/width aspect ratio of at least 10, and the one or more fill trenches have been filled by depositing the high-density material into the fill trenches in an atomic layer deposition (ALD) process.

Abstract: A scanning device includes a planar scanning mirror disposed within a frame and having a reflective upper surface. A pair of flexures have respective first ends connected to the frame and respective second ends connected to the mirror at opposing ends of a rotational axis of the mirror. A rotor including a permanent magnet is disposed on the lower surface of the mirror. A stator includes first and second cores disposed in proximity to the rotor on opposing first and second sides of the rotational axis and first and second coils of wire wound respectively on the cores. A drive circuit drives the first and second coils with respective electrical currents including a first component selected so as to control a transverse displacement of the mirror and a second component selected so as to control a rotation of the mirror about the rotational axis.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: Methods for manufacturing semiconductor structures are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate and forming a source/drain structure over the fin structure. The method for manufacturing a semiconductor structure further includes forming a metallic layer over the source/drain structure and forming an oxide film on a sidewall of the source/drain structure. In addition, the oxide film and the metallic layer are both in direct contact with the source/drain structure.

Abstract: A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first and second layers differ. The first and second pluralities of conductive lines are each lithographically defined. The first and second pluralities of conductive lines are insulated from each other. The memristive interlayer connectors are memristively coupled with a first portion of the first plurality of conductive lines and memristively coupled with a second portion of the second plurality of conductive lines. The memristive interlayer connectors are thus sparsely coupled with the first and second pluralities of conductive lines. Each memristive interlayer connector includes a conductive portion and a memristive portion.

Abstract: A MEMS device and a MEMS device manufacturing method are provided for suppressing damage to device parts. An exemplary method of manufacturing a resonance device includes radiating laser light from a bottom surface side of a second substrate to form modified regions inside the second substrate along dividing lines of a first substrate, which has device parts formed on a top surface thereof, and the second substrate, the top surface of which is bonded to the bottom surface of the first substrate via bonding portions. The method further includes dividing the first and second substrates along the dividing lines by applying stress to the modified regions. The bonding portions are formed along the dividing lines and block the laser light.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.

Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

Abstract: A tunnel barrier layer includes a non-magnetic oxide, wherein a crystal structure of the tunnel barrier layer includes both an ordered spinel structure and a disordered spinel structure.

Abstract: A micro-electromechanical (MEM) relay and its fabrication process. The MEM relay includes a movable actuator electrode anchored to a substrate with two cantilever beams. Below the actuator electrode, there are three fixed electrodes. These three electrodes are the gate, the input, and the output contacts. The square base of the actuator electrode, and the square gate electrode below it, form an electrostatic parallel-plate actuator. When a voltage is applied between the actuator electrode and the gate electrode, the actuator electrode is pulled-down due to electrostatic attraction closing the relay. When the voltage is removed, the cantilever beams act as springs opening the relay.

Abstract: A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

Abstract: A semiconductor device includes a substrate, a plurality of fins on the substrate, and an isolation region between the fins. Each of the fins includes a semiconductor material region and an impurity region disposed in the semiconductor material region. The impurity region has an upper surface below an upper surface of the isolation region.

Abstract: A MEMS structure including a latch, a first lever, and a second lever. The first lever is designed to move past the latch as a result of flexure in the event of a change in a parameter in a first direction, and to latch in place at the latch if a change in the parameter in a second direction different than the first direction subsequently takes place. The second lever is designed to move past the first lever as a result of flexure in the event of the change in the parameter in the second direction, and to latch in place at the first lever if a change in the parameter in the first direction takes place after the change in the parameter in the second direction.

Abstract: The present invention discloses a bidirectional ultraviolet light emitting diode (UV LED) based on N—ZnO/N—GaN/N—ZnO heterojunction as well as its preparation method. The LED includes: N—ZnO microwires, a N—GaN film, a PMMA protective layer and alloy electrodes; and its preparation method includes the following steps: lay two N—ZnO microwires on the N—GaN film, then spin-coat a PMMA protective layer on the film to fix the N—ZnO microwires until the PMMA protective layer spreads over the N—ZnO microwires, and then place the film on a drying table to solidify the PMMA protective layer; then etch the PMMA protective layer with O2 to expose the N—ZnO microwires, and prepare alloy electrodes on different N—ZnO microwires to construct a N—ZnO/N—GaN/N—ZnO heterojunction to constitute a complete device. The present invention constructs an N/N/N symmetrical structure; the device is composed of N—ZnO and N—GaN, emits light in the ultraviolet region and has a small turn-on voltage.

Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

Abstract: A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Abstract: A micro structure with a substrate having a top surface; a first electrode with a horizontal orientation parallel to the top surface of the substrate, wherein the first electrode is embedded within the substrate so that a top surface of the first electrode coincides with the top surface of the substrate; a dielectric layer arranged on the top surface of the first electrode; and a second electrode arranged above the dielectric layer.