Abstract: A buffer circuit for rotating outstanding transactions. A buffer circuit includes a buffer and a command update circuit. The buffer may be configured to store packet commands that belong to a respective virtual channel of a plurality of virtual channels. The packets may be stored in the buffer to await transmission upon a peripheral bus. Once a given packet is selected for transmission, a peripheral bus cycle corresponding to the given packet command may be generated upon the peripheral bus. The command update circuit may be configured to generate a modified packet command in response to receiving a partial completion indication associated with the peripheral bus cycle. The command update circuit may also be configured to cause the modified packet command to be stored within the buffer.

Abstract: A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or transactions. In particular, instead of simply dedicating a portion of the system resources to requests and the remaining portion to responses, a minimum amount of resources are reserved for responses and a minimum amount for requests, while the remaining resources are dynamically shared between both types of messages. The method and architecture of the present invention allows for more efficient use of system resources, while avoiding deadlock conditions and ensuring a minimum service rate for requests.

Abstract: The present invention is, in one embodiment, a method for efficiently and reliably communicating button presses electronically on a network from one or more push button nodes each having at least one push button, to a master node. This method includes steps of: generating status messages indicative of a push button states at each of push button node; communicating the status messages to the master node via the network; determining, at the master node, the state of the push buttons at each of the push button nodes from the communicated status messages; and triggering a response of the master node, in accordance with the statuses of the push buttons determined from the communicated status messages.

Abstract: Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from a host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that are transferred between the buffer and the storage medium, and a second register that stores a value for tracking a number of data units that are transferred between the host device and the buffer. A data unit is transferred between the buffer and the storage medium if the value in the first register is within a predetermined range. Similarly, a data unit is transferred between the buffer and the host device if the value in the second register is within a predetermined range.

Abstract: A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system.

Abstract: A method for removing unwanted header information from a frame in a network is disclosed. It includes: storing beginning bytes of the frame in a first buffer and remaining bytes in a second buffer, where a size of the first buffer is smaller than the second buffer; determining that the unwanted header information is stored in the first buffer; copying bytes of the frame after the unwanted header information that are stored in the first buffer over the unwanted header information; reporting a number of bytes of the frame stored in the first buffer to be retrieved; and retrieving the reported number of bytes of the frame stored in the first buffer and the bytes of the frame stored in the second buffer. The copying of bytes occurs exclusively in the first buffer. Thus, removing the unwanted header information requires fewer processor cycles and minimizes latency in the packet receive process.

Abstract: A keyboard selectively operable to convey data to and from a host or personal computer (PC) through a universal serial bus (USB) port and/or a personal system/2 (PS/2) port. The keyboard is preferably connected to both the USB port and PS/2 port on the host or PC, if available. Preference is given to communicating data from the keyboard to the host or PC through the PS/2 port. However, if the PS/2 port is unavailable, not connected, or inoperative, the keyboard data are communicated to the host or PC through the USB port (assuming that it is available, operative, and connected). As soon as the PS/2 port on the host or PC is again connected to the keyboard, such data will again be communicated through the PS/2 port. In addition, the keyboard includes auxiliary USB ports to which USB-capable peripheral devices can be connected. USB data can then be communicated between the PC and the USB-capable peripheral devices via the keyboard and its connection to the USB port on the host or PC.

Abstract: The invention relates to a Universal Serial Bus (USB) with two wireless communication hubs (USB hubs). One of these hubs is connected to a first host computer, and both USB hubs are connected to a plurality of I/O devices. Each USB hub includes a wireless adapter and an antenna connected to the wireless adapter. The wireless adapter of each USB hub comprises a transmitting/receiving unit for transmitting data via the antenna to the wireless adapter of the other USB hub or receiving data via the antenna from the wireless adapter of the other USB hub. The wireless adapter also comprises a wireless dual port, which is automatically configured upstream or downstream when the first host computer is connected to one of the USB hubs.

Abstract: A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

Abstract: In order to connect a control signal processing system of a device, which does not have a control signal processing system for coding and processing a control signal, to a control signal processing system for coding and processing such a control signal, circuitry is added to the existing control signal processing systems for delivering mutual signals between a control signal processing system (1) for coding and processing control signals such as VISCA and a control signal processing system for processing a signal representing information as a signal level value. It thus becomes possible to connect control signals of a device (30, 37, 38) which does not have a control signal processing system for coding and processing the control signal to a control signal processing system (1) for coding and processing the control signal.

Abstract: Methods and systems for overlapping data flow within an extended copy command over a network, including, at a router in a network: receiving an extended copy command from a first host to a first target device; determining an initial network status if the network status is unknown; initializing a set of read-write parameters; and executing the extended copy command for a first segment of the extended copy command, and for one or more subsequent segments, by overlapping one or more read and one or more write commands of the extended copy command.

Abstract: A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.

Abstract: A data transfer apparatus includes a reception unit for receiving data from the first external device; a storage unit for storing the data received by the reception unit; an output unit for receiving data and outputting the data to a second external device; a retransmission request receiving unit for receiving a retransmission request signal from the second external device; and a transfer control unit for having a first transfer performed when the receiving unit has received data from the first external device, the first transfer transferring the data using direct memory access (DMA) directly to both the output unit and the storage unit in parallel, and having a second transfer performed when retransmission request receiving unit has received the retransmission request signal, the second transfer transferring data, which has already been stored in the storage unit by the first transfer, to the output unit.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: The present invention provides for a dual sequencer for use in a peripheral storage device system, as well as a new protocol for data retrieval/storage in peripheral storage device systems. The system provides for more efficient media storage/retrieval and addresses the issue of channel latencies in media storage/retrieval systems.

Abstract: Methods and apparatus are provided for transferring data words from a source to a destination. The apparatus includes a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition, and read control logic for reading the first number of data words from the datapath buffer in response to a first destination transfer condition and for reading the second number of data words from the datapath buffer in response to a second destination transfer condition.

Abstract: A virtual channel buffer bypass in a computer system input/output node. A control unit of an input/output node for a computer system includes a buffer circuit configured to receive control commands. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. The buffer circuit may also be configured to determine whether each of the plurality of buffers is empty prior to storing a particular control command corresponding to a given one of the plurality of buffers. In addition, the buffer circuit may be configured to cause the particular control command to bypass the given one of the plurality of buffers in response to determining that each of the plurality of buffers is empty.

Abstract: An arbiter apparatus for selecting an agent to use a shared resource such as memory. A normal round robin list is utilized in the selection process during boot operation. During the initialization process, a dynamic list is generated in accordance with system requirements. The dynamic list selection process may take any of several forms. In a first mode, it may select only priority listed agents, any one of which may be repeated during a given cycle of selection. In a second mode, it may select a designated buddy agent when the selected priority agent is idle. In either mode, and in accordance with a set of priority selection rules, one or more lowest priority default agents may be given access when the designated higher priority agents for a given list entry slot are idle.

Abstract: The method of the present invention enables a SCSI repeater to dynamically determine the speed of an input device and adjust the repeater's output speed accordingly. Thus, the SCSI repeater can transparently connect independent SCSI buses that are connected to different devices with different requirements, preventing the slowest device from limiting the speed of the fastest device.