Abstract: A verification device is configured to supply operation power to a verification target device in order to communicate with the verification target device, and perform verification of the verification target device. The verification device includes: a detection unit configured to detect a value of a current that flows in the verification device due to the operation power being supplied to the verification target device; a determination unit configured to determine whether or not the value of the current is greater than a threshold value; and a verification unit configured to verify authenticity of the verification target device according to whether or not the value of the current is greater than the threshold value.

Abstract: A pre-boot screen can be accessed remotely. A remote access BIOS module can be employed on a computing system to logically split a GPU into a local screen rendering part and a remote access part and to logically split GPU memory into a local screen memory region and a remote access memory region. The remote access part of the GPU can access a pre-boot screen that has been copied to the remote access memory region and create network packets with payloads containing the pre-boot screen. The remote access part can then cause the network packets to be transferred to a NIC for delivery to a remote computing system. A remote access application on the remote computing system can extract and display the pre-boot screen. The remote access application can relay any user input back to the remote access BIOS module which can then cause the user input to be implemented locally.

Abstract: Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

Abstract: One embodiment provides a method, including: receiving, at an information handling device in a low power mode, a wake indication; waking, responsive to the receiving, the information handling device from the low power mode; receiving, at the awoken information handling device, context data obtained by at least one other device; and performing an action based on the received context data. Other aspects are described and claimed.

Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.

Abstract: Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

Abstract: A multi-power management system and an operation method for the multi-power management system are provided. The multi-power management system includes multiple adapters and a power supply circuit. The adapters respectively provide multiple powers. The power supply circuit receives multiple input power values of the adapters, and calculates multiple input power value contribution ratios of the adapters according to the input power values. The power supply circuit further provides a control signal according to a sum of the output current values of multiple output current values of the powers and the input power value contribution ratios. The adapters adjust the output current values and multiple output voltage values respectively in response to the control signal.

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

Abstract: A method and computer system are disclosed for controlling a system boot of the computer system. Both involve determining that a chassis of the computer system was opened, determining whether the opening of the chassis was authorized, and controlling the system boot of the computer system based on whether the opening of the chassis was authorized.

Abstract: Systems and methods for backlight dimming via buck-boost conversion in an information handling system (IHS) are described. In some embodiments, an IHS may include an embedded controller (EC), and a memory coupled to the EC, the memory having program instructions stored thereon that, upon execution, cause the EC to: determine a characteristic of a display having a backlight; and dim the display by controlling a buck-boost converter to reduce a voltage applied to the backlight.

Abstract: In one embodiment, a method includes grouping a plurality of ports at power sourcing equipment receiving pulse power and transmitting power from the group of ports at the power sourcing equipment to a power interface module operable to combine the power and provide an AC (alternating current) outlet configured to provide AC power to one or more devices.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

Abstract: A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the operating voltages or clock frequencies provided to the one or more islands in response to a change in numbers of active memory barriers in the one or more islands. In some cases, the operating voltage or clock frequency provided to an island is increased in response to the number of active memory barriers in the island decreasing. The operating voltage or clock frequency provided to the island is decreased in response to the number of active memory barriers in the island increasing.

Abstract: An apparatus, a system, and a method for allocating power to a graphics processing unit, where the apparatus includes a frame rate detection module configured to detect a frame rate of current image data to-be-displayed, and a power allocation module configured to: determine whether the frame rate is lower than a preset frame rate threshold; if the frame rate is lower than the preset frame rate threshold, determine that displaying of the image data is in a frame freezing state; determine, in response to the frame freezing state, whether a graphics processing unit reaches a power bottleneck state; and if determining that the graphics processing unit reaches the power bottleneck state, increase power of the graphics processing unit and reduce power of another module related to the displaying.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various checks and combinations of checks including installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: A sensor circuit in a computer system measures a frequency of an oscillator circuit and uses the measured frequency to determine an operating condition of the computer system. The accuracy of the operating condition is limited by various sources of noise, including device noise, that introduce error into frequency measurements, limiting the accuracy to which the frequency of the oscillator signal may be measured. To improve the accuracy of the frequency measurement of the oscillator signal, the sensor circuit disables the oscillator between successive measurements, in order to reduce the correlation of error between the successive measurements. The sensor circuit combines the multiple measurement results to determine the frequency of the oscillator signal to a higher degree of accuracy, thereby improving the accuracy to which the operating condition is determined.