Abstract: An array substrate and a flexible display panel are provided. The array substrate is in a bending region and includes a base; an inorganic layer formed on the base, wherein at least one hollowing-out region is disposed in the inorganic layer, and the hollowing-out region is non-filled or filled with an organic matter; and a metal layer formed on the inorganic layer and connected to layers on a bottom of the inorganic layer by at least one via hole encircled by the at least one hollowing-out region. When the flexible display panel is bent, the at least one hollowing-out region provides a good channel for releasing stress in the inorganic layer and improves the bending performance of the flexible display panel.

Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.

Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

Abstract: Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.

Abstract: An array substrate, a method for manufacturing the array substrate and a display device are provided. The array substrate includes a substrate, an organic film layer and a passivation layer; the organic film layer is arranged between the substrate and the passivation layer; a venting hole is formed in the passivation layer.

Abstract: A heat processing system is disclosed. The heat processing system includes an enclosure, a heater, and a plurality of valves disposed on the enclosure. The heater is used to increase temperature within the enclosure. The plurality of valves have different sizes to uniformly and efficiently control the cooling within the enclosure.

Abstract: A semiconductor device including a substrate having a major surface. The semiconductor device further includes a dielectric material on the major surface of the substrate. The semiconductor device further includes a first plurality of fins extending from the major surface of the substrate, wherein the dielectric material surrounding each fin of the first plurality of fins has a first thickness. The semiconductor device further includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, the dielectric material surround each fin of the second plurality of fins has a second thickness, and the second thickness is different from the first thickness.

Abstract: A nonvolatile resistive switching memory comprising an insulating substrate, a lower electrode, a lower graphene barrier layer, a resistive switching functional layer, an upper graphene barrier layer, and an upper electrode, wherein the lower and/or the upper graphene barrier layer is/are capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer under an applied electric field.

Abstract: A color control member includes a substrate including a first pixel area and a second pixel area; a first color conversion layer converting incident light on the first color conversion layer to light of a first color, the light of the first color being emitted from the first color conversion layer and through the first pixel area; a second color conversion layer converting incident light on the second color conversion layer to light of a second color, the light of the second color being emitted through the second color conversion layer and through the second pixel area; and a partition wall disposed between the first color conversion layer and the second color conversion layer to correspond to a light-blocking area of the substrate in which the light emitted from the first color conversion layer or the second color conversion layer is blocked from being emitted to the other thereof.

Abstract: The objective of the present invention is to provide a technique that ensures conduction between a gate terminal of a semiconductor switching element and a wiring layer in a semiconductor device formed with a wiring layer inside a ceramic layer. This semiconductor device comprises: a wiring layer that is inside a ceramic layer formed above an insulation layer; and a metal layer for connecting terminals from the semiconductor switching element other than the gate terminal. The wiring layer and the gate terminal from the semiconductor switching element are connected electrically via a connection part formed from a conductive material. The connection part protrudes more than the metal layer toward the semiconductor switching element.

Abstract: Provided is a display apparatus including a display module having a folding region and a plurality of non-folding regions adjacent to the folding region and including a display surface configured to display an image, and a support member below the display module and supporting the display module, wherein the display module is operated in a plurality of modes, and the plurality of modes includes a first mode in which the folding region has a first curvature radius and is folded in a first bending direction which surrounds a virtual first bending axis defined below the display module and a second mode in which the folding region has a second curvature radius and is folded in a second bending direction which surrounds a virtual second bending axis defined above the display module, wherein the first curvature radius is greater than the second curvature radius.

Abstract: A display panel and a manufacturing method thereof are provided. The method includes: forming a flexible substrate on a display area and a welding area of a glass substrate; sequentially forming a switch array layer and an organic light-emitting display layer on the flexible substrate and an edge area of the glass substrate; patterning the switch array layer, such that a switching element and a metal wire are respectively formed on the display area and the welding area, and a portion of the switch array layer and the organic light-emitting display layer on the edge area are removed.

Abstract: A high voltage depletion mode MOS device with adjustable threshold voltage includes: a first conductive type well region; a second conductive type channel region, wherein when the channel region is not depleted, the MOS device is conductive, and when the channel region is depleted, the MOS device is non-conductive; a second conductive type connection region which contacts the channel region; a first conductive type gate, for controlling the conductive condition of the MOS device; a second conductive type lightly doped diffusion region formed under a spacer layer of the gate and contacting the channel region; a second type source region; and a second type drain region contacting the connection region but not contacting the gate; wherein the gate has a first conductive type doping or both a first and a second conductive type doping, and wherein a net doping concentration of the gate is determined by a threshold voltage target.

Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.

Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.

Abstract: In a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The transistor includes an oxide semiconductor film over a first insulating film; a second insulating film over the oxide semiconductor film; a metal oxide film over the second insulating film; a gate electrode over the metal oxide film; and a third insulating film over the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The source region and the drain region contain one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a first insulating part provided in the first semiconductor region, a first electrode provided in the first semiconductor region, the first insulating part disposed between the first electrode and the first semiconductor region, a second insulating part provided on the first electrode, a gate electrode provided on the second insulating part, a gate insulating part provided between the gate electrode and the second semiconductor region, and a second electrode provided on the second semiconductor region and on the third semiconductor region, and is electrically connected to the second semiconductor region, the third semiconductor region, and the first electrode.

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.