Abstract: A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.

Abstract: The invention is directed to a method for manufacturing a field plate of a high voltage device. The field plate is located on a drift region of a substrate, wherein an isolation structure is located on the drift region. The method comprises steps of forming a first dielectric layer over the substrate and then forming a first patterned conductive layer on the first dielectric layer, wherein the first patterned conductive layer is located over the isolation structure and exposes a portion of a top surface of the first dielectric layer. The exposed portion of the first dielectric layer is removed until a top surface of the isolation structure so as to form a plurality of vertical fin-type dielectric bottoms.

Abstract: The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a dicing process, a miniaturized image sensor module using this wafer level chip size package (WL-CSP) and a method thereof. The CMOS image sensor module using a wafer level chip size package technology according to the present invention comprises: an image sensor chip wafer having a partition with a lattice structure formed at portions except an image sensing area; and a glass wafer with an IR filter coating layer and a metal electrode; and wherein the image sensor chip wafer and the glass wafer form an electric contact and a chip sealing by a flip-chip bonding; and wherein a solder bump and a non solder bump are formed after a metal wiring is rearranged on a lower surface of the glass wafer.

Abstract: An alignment mark for a plasma display panel (PDP). The alignment mark comprises a first and a second alignment patterns installed on a front and a rear substrate respectively. The second alignment pattern on the non-display area is simultaneously formed with the rib barrier formation on the display area of the rear substrate, wherein the second alignment pattern is hexagonal-honeycomb. The first alignment pattern on the front substrate is simultaneously formed with the non-transparent material fabrication, such as a bus electrode or black matrix fabrication, and corresponds to a space within the second alignment pattern. The first alignment pattern comprises at least one line segment, parallel to at least one side of the hexagonal honeycomb pattern on the rear substrate with a predetermined distance therebetween.

Abstract: A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid. The structure optionally further includes metal pads to form an electrokinetic pump.

Abstract: An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active region columns. An interlayer insulating film formed as a layer below an upper wiring is provided on the active region and the control electrodes. Conductive sections that electrically connect the upper wiring and the active region are respectively provided on the concave portions on the active region rows.

Abstract: A junction structure, and a semiconductor device including the same, for a junction of a terminal pad and solder, including an underlying base on which said terminal pad is formed; a nickel layer disposed on the terminal pad; a palladium layer or a gold layer disposed on the nickel layer; the solder; and a zinc system material layer provided between the palladium layer or the gold layer and the solder. The terminal pad and the solder may be provided in a semiconductor device in which the terminal pad lies inside the semiconductor device, and the zinc system material layer is formed between the terminal pad and the solder. The terminal pad may be provided over a substrate, the solder may be provided in the semiconductor device, and the zinc system material layer is then formed between the terminal pad of the substrate and the solder of the semiconductor device.

Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to simulate the components from the substrate. Prior to the simulating step the components can be tested and burned-in while they remain on the substrate.

Abstract: A TFT substrate comprises a substrate, a gate electrode and a lower electrode of a capacitor formed thereon, a first insulating layer formed thereon, a channel layer above the gate electrode and a lower layer of an upper electrode of the capacitor, a channel protection layer formed on an intermediate part of said channel layer and a capacitor protection layer formed on a connection region of the lower layer, source/drain electrodes formed on said channel layer and an upper layer of the upper electrode of the capacitor formed on the lower layer and covering the capacitor protection layer, a second insulating layer covering them, a first connection hole exposing the source electrode and a second connection hole exposing a connection region of said upper layer, which are penetrating the second insulating layer, and a pixel electrode formed thereon.

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract: A power transistor includes a leadframe and a semiconductor chip arranged on the leadframe. The top side of the semiconductor chip has a drain contact-making layer, and the underside of the semiconductor chip has a source contact-making layer. The source contact-making layer bears directly on the leadframe. A gate contact-making layer is provided on the top side of the semiconductor chip. The gate contact-making layer is electrically connected via at least one trench filled with conductive material to gate zones provided in the lower region of the semiconductor chip.

Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

Abstract: The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.

Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.

Abstract: A CMOS image sensor and a manufacturing method are disclosed. The gates of the transistors are formed in the active region of the unit pixel, and a diffusion region for the photo diode is defined by an ion implantation of impurities to the semiconductor substrate. The patterns of the photoresist that are the masking layer against ion implantation are formed on the semiconductor substrate in such a manner that they have the boundary portion of the isolation layer so as not to make the boundary of the defined photo diode contact with the boundary of the isolation layer. Damages by an ion implantation of impurities at the boundary portion between the diffusion region for the photo diode and the isolation layer are prevented, which reduces dark current of the COMS image sensor.

Abstract: A method for integrating three bipolar transistors into a semiconductor body, multilayer component, and semiconductor arrangement is provided. A tendency toward thyristor-like behavior of the multilayer semiconductor arrangements with the three bipolar transistors is suppressed with the aid of a heterojunction. The high frequency characteristics and the blocking capability of the circuit of the three bipolar transistors is made more flexible, while the capability of an input signal to control an output signal is maintained.

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: Provided are an n-type carbon nanotube field effect transistor (CNT FET) and a method of fabricating the n-type CNT FET. The n-type CNT FET may include a substrate; electrodes formed on the substrate and separated from each other; a CNT forrmed on the substrate and electrically connected to the electrodes; a gate oxide layer formed on the CNT; and a gate electrode formed on the gate oxide layer, wherein the gate oxide layer contains electron donor atoms which donate electrons to the CNT such that the CNT may be n-doped by the electron donor atoms.