Abstract: A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel insulator material comprises MgO and the magnetic electrode material comprises Co and Fe. B is proximate opposing facing surfaces of the tunnel insulator material and the magnetic electrode material. B-absorbing material is formed over a sidewall of at least one of the magnetic electrode material and the tunnel insulator material. B is absorbed from proximate the opposing facing surfaces laterally into the B-absorbing material. Other embodiments are disclosed, including magnetic tunnel junctions independent of method of manufacture.

Abstract: An image sensor device with layered structures is disclosed, which includes a carrier wafer, image sensing structures and insulating layers. The carrier wafer has a pixel area and a peripheral area. Each of the image sensing structures has a first portion in the pixel area for sensing incident light in a specific wavelength band and a second portion in the peripheral area. Each of the insulating layers is disposed between adjacent stacked image sensing structures, such that crosstalk issues between adjacent diffusion layers are avoided for higher isolation, thereby improving photo sensing quality.

Abstract: A quasi-crystal organic light-emitting display panel including a first electrode layer, an organic light-emitting layer, a second electrode layer, a buffer layer, a 10-fold quasi-crystal layer and a package cover is provided. The organic light-emitting layer is located on the first electrode layer. The second electrode layer is located on the organic light-emitting layer. The buffer layer is located on the second electrode layer. The 10-fold quasi-crystal layer is located on the buffer layer. The package cover is located on the 10-fold quasi-crystal layer. A method for simulating optical efficiency of the quasi-crystal organic light-emitting display panel is also provided.

Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

Abstract: A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided.

Abstract: A device includes a seed layer, a magnetic track layer disposed on the seed layer, an alloy layer disposed on the magnetic track layer, a tunnel barrier layer disposed on the alloy layer, a pinning layer disposed on the tunnel barrier layer, a synthetic antiferromagnetic layer spacer disposed on the pinning layer, a pinned layer disposed on the synthetic antiferromagnetic spacer layer and an antiferromagnetic layer disposed on the pinned layer, and another device includes a seed layer, an antiferromagnetic layer disposed on the seed layer, a pinned layer disposed on the antiferromagnetic layer, a synthetic antiferromagnetic layer spacer disposed on the pinned layer, a pinning layer disposed on the synthetic antiferromagnetic layer spacer, a tunnel barrier layer disposed on the pinning layer, an alloy layer disposed on the tunnel barrier layer and a magnetic track layer disposed on alloy layer.

Abstract: A package for a chemical sensor including an encapsulation and a pressure balancing structure is disclosed. The encapsulation encapsulates a chemical sensor and has a hole for exposing a chemical sensitive part of the chemical sensor. The pressure balancing structure balances pressure applied to the chemical sensor at the chemical sensitive part.

Abstract: A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps.

Abstract: Light-emitting devices having a multiple quantum well (MQW) pin diode structure and methods of making and using the devices are provided. The devices are composed of multilayered semiconductor heterostructures. The devices include one or more interfacial layers of a material that allows current tunneling through lattice mismatched heterogeneous junctions at the interfaces between the intrinsic active region and the p-type and/or n-type doped charge injection layers.

Abstract: If the threshold of a thin film transistor is depleted, a leak-induced voltage drop takes place and the desired voltage cannot be obtained. Depending on the severity of the phenomenon, the thin film transistor may fail to function. This disclosure offers a thin film transistor circuit having a first transistor connected to a low voltage, and a second transistor connected to the gate of the first transistor. When the gate voltage of the second transistor is changed from the high level to the low level, the gate voltage of the first transistor is brought to a voltage level lower than the low voltage.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure and a source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device structure further includes an isolation layer between the source/drain structure and the semiconductor substrate.

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract: A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of multi-plugs structure. The silicon-containing layers stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of multi-plugs structure has plural plugs each corresponding to and connected with one of the silicon-containing layers. Each of the metal strapped word lines is connected to the plugs that are connected to the identical silicon-containing layer.

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract: A patterning method and a patterned material layer are provided. After providing a substrate including a material layer, a hard mask layer including trenches extending in a first direction is formed over the material layer. A filling material layer is formed on the hard mask layer to cover the hard mask layer and fills in the trenches. A mask layer in a grid pattern is formed on the filling material layer. The mask layer includes first grid lines extending in the first direction and second grid lines extending in a second direction, and each of the underlying trench is located between two most adjacent first grid lines. The material layer is etched with the mask layer as an etching mask to form a patterned material layer including a plurality of first holes and a plurality of second holes.

Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

Abstract: A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.