Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Abstract: A method and apparatus for coupling a MEMS device to a substrate is disclosed. The method includes providing a substrate with a conductor disposed over the substrate, adhering the MEMS device to the substrate, wherein a first elastomer adheres the MEMS device to the substrate. The MEMS device is electrically connected to the conductor using a wire bond.

Abstract: A nitride semiconductor epitaxial wafer includes a substrate, and a nitride semiconductor layer formed on the substrate, the nitride semiconductor layer including a (002) plane in an upper surface thereof. An in-plane dispersion of a full width half maximum (FWHM) of an X-ray rocking curve in the (002) plane or a (100) plane of the nitride semiconductor layer is not more than 30%. The wafer is not less than 100 ?m in thickness and not less than 50 mm in diameter.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a first substrate having an electronic device mounted on both surfaces thereof; and a second substrate bonded to one surface of the first substrate and including an insertion part in which the electronic device mounted on one surface of the first substrate is inserted, wherein the second substrate includes a ground and a shielding wall which is formed along an inner wall or an outer wall of the second substrate.

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

Abstract: A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.

Abstract: The present invention is capable of suppressing a variation in the characteristics of a semiconductor device. In a conductor pattern CPA and a conductor pattern CPB arranged so as to run side by side with each other, the conductor pattern CPA is divided into a first portion P1 (A) and a second portion P2 (A), and the conductor pattern CPB is also divided into a first portion P1 (B) and a second portion P2 (B). The first portion P1 (A) of the conductor pattern CPA and the second portion P2 (B) of the conductor pattern CPB are formed by first patterning using the same first mask, while the second portion P2 (A) of the conductor pattern CPA and the first portion P1 (B) of the conductor pattern CPB are formed by second patterning using the same second mask.

Abstract: A display device includes an array substrate including a display area and a non-display area, a driving circuit chip disposed on the non-display area and including a bottom surface, a top surface, a first pair of side surfaces extending in a first direction, and a second pair of side surfaces extending in a second direction perpendicular to the first direction, and first, second, and dummy bumps, each disposed on the bottom surface in a single column along the first direction, in which the dummy bumps include first and second dummy bump groups disposed between the first and second bumps along the first direction, the dummy bumps in the first dummy bump group are spaced apart from each other by a first pitch, and the dummy bumps in the second dummy bump group are spaced apart from each other by a second pitch different from the first pitch.

Abstract: An input device for capacitive sensing. The input device includes a plurality of sensor electrodes for capacitive sensing disposed in a first layer and within a sensor electrode region comprising an areal extent of the plurality of sensor electrodes. The input device also includes a plurality of routings disposed in a second layer and within a border region of the sensor electrode region, the plurality of routings layered with a first set of two or more of the plurality of sensor electrodes in the border region and electrically coupled to a second set of two or more of the plurality of sensor electrodes, wherein the second set of two or more of the plurality of sensor electrodes includes zero, one, or two of the sensor electrodes included in the first set of two or more of the plurality of sensor electrodes.

Abstract: A wiring substrate includes a heat spreader, a first insulating layer provided on the heat spreader via an adhesion layer, the first insulating layer, a plurality of through wirings formed to fill through holes provided at the first insulating layer, respectively, a thermal diffusion wiring provided on the first insulating layer so as to be connected to the through wirings, the thermal diffusion wiring being configured not to be electrically connected to a semiconductor device, an electrical connection wiring provided on the first insulating layer, the electrical connection wiring being configured to be electrically connected to the semiconductor device, wherein the heat spreader is provided with a projection portion, made of a composition same as the heat spreader, at a surface of the heat spreader on which the adhesion layer is formed, the projection portion being aimed at least at an area overlapping the through wirings in a plan view.

Abstract: Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side.

Abstract: In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.

Abstract: A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Abstract: Embodiments relate to a light emitting device package including a package body, a light emitting structure disposed on the package body, the light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, the light emitting structure being divided into at least two light emitting cells, a support substrate located between the package body and the light emitting structure, a first electrode and a second electrode connected to each of the light emitting cells and fluorescent substances disposed respectively on the light emitting cells. At least two layers among the first conductive semiconductor layer, the active layer and the second conductive semiconductor layer included in each of the light emitting cells next to each other are electrically separated from each other.

Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.

Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.

Abstract: A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.

Abstract: A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

Abstract: A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.