Abstract: A lead frame for a semiconductor device, made of a copper alloy, capable of preventing the creation of delamination between encapsuling resin and attributable to a lead frame without sacrificing the wire bondability and, a process for producing the lead frame and a semiconductor device using the lead frame. According to the present invention, (1) there is provided a lead frame for a plastic molded type semiconductor device, made of a copper alloy material partially plated with at least one noble metal, for wire bonding or die bonding purposes, selected from silver, gold, and palladium, wherein the whole area or a predetermined area of the surface of the copper at least on its side to be contacted with a encapsuling resin has a thin noble metal plating of at least one member selected from silver, gold, platinum, and palladium.

Abstract: A semiconductor device includes a substrate having a first surface, a second surface and at least one conductor part which are exposed at both the first and second surfaces of the substrate, a semiconductor chip provided on the first surface of the substrate and having a plurality of electrode pads, a plurality of leads, a plurality of bonding-wires electrically connecting the leads and the conductor parts to corresponding ones of the electrode pads of the semiconductor chip, and a resin package encapsulating the semiconductor chip, a part of the leads, and the substrate so that the conductor parts are exposed at the second surface of the substrate.

Abstract: An integrated circuit die or chip may be positioned within an integrated circuit package by providing a spacer connected to the die and extending upwardly therefrom. When the die is overmolded, the spacer contacts the mold and spaces the die with respect to the mold. By forming the spacer using conventional wire bonding techniques, no additional process steps are necessary in forming the spacer and no additional parts are needed. The spacer wire bonds may be formed with wires which extend upwardly above the remaining wires, protecting the remaining wires from being contacted by the mold or from being positioned too close to the upper surface of the resulting molded package.

Abstract: A ball grid array semiconductor package includes an insulative base material; circuitry metallizations formed on a first surface of the material, each metallization having a grid pad electrode; and a semiconductor chip mounted on the first surface and electrically connected to the circuitry metallizations. The base material is opened from a second surface of the base material at a location under each grid pad electrode; and each opening confines a portion of a solder ball which is in melt-fixed connection to a back side of each grid electrode.

Abstract: One embodiment of the instant invention is a charge-induced damage protection device (100 or 500) for protecting a semiconductor device (200) which is formed on a common substrate with the protection device, the protection device comprising: a region in the substrate; and wherein the region is accessible to electromagnetic energy during processing in which charges may collect on conductive material such that the protective device turns on at a lower voltage due to introduction of the electromagnetic energy to the region so as to protect the semiconductor device from the charge-induced damage. Preferably, the protection device is selected from the group consisting of: a diode, a thyristor, a bidirectional thyristor, a bipolar transistor, and a polymer that becomes more conductive upon being illuminated by electromagnetic energy.

Abstract: A chip scale ball grid array for integrated circuit packaging having a nonpolymer layer or support structure positioned between a semiconductor die and a substrate. The nonpolymer support structure acts to increase circuit reliability by reducing thermal stress effects and/or by reducing or eliminating formation of voids in an integrated circuit package. A nonpolymer support structure may be a material, such as copper foil, having sufficient rigidity to allow processing of chip scale package in strip format.

Abstract: A semiconductor light-emitting element comprising a monocrystal substrate; a buffer layer formed directly on the monocrystal substrate and comprising a monocrystal Al.sub.x Ga.sub.1-x N layer (0<x<1); and element-forming layer formed on the buffer layer and comprising Al.sub.x Ga.sub.y In.sub.1-x-y N (0.ltoreq.x+Y.ltoreq.1, 0.ltoreq.x, Y.ltoreq.1). The half-value width of an X-ray rocking curve of the buffer layer should preferably be 5 minutes or less, more preferably 90 seconds or less.

Abstract: An apparatus for removing heat from the backside of a packaged flip chip. In one embodiment, the top side of an integrated circuit die is mechanically and electrically coupled to the top surface of a package substrate via a plurality of solder bump interconnections. A heatsink is supported above the backside surface of the die and the package substrate by standoffs. The height of the standoffs is selected to produce a gap between the heatsink and the backside of the die. The gap is filled with a highly conductive heat transfer medium, such as a thermal grease, to provide a heat path between the die and the heatsink. A spring clip flexibly attaches the heatsink to the package by providing a force to the heatsink to seat the standoffs against the top surface of the package substrate.

Abstract: In a resin molded semiconductor device, a metal lead frame includes an island and leads, and the leads have bulged terminal portions. Also, a semiconductor chip is mounted on the island, and external terminals are adhered to the bulged terminal portions opposite to the semiconductor chip. Further, an envelope of resin encapsulates the metal lead frame, the semiconductor chip and a part of each of the external terminals.

Abstract: A semiconductor device comprises a first semiconductor layer formed of a Group III-V semiconductor layer or a II-VI semiconductor layer; and a second semiconductor layer formed of a Group IV semiconductor layer or a Group II-VI semiconductor layer which is different material from the first semiconductor layer and formed in heterojunction with the first semiconductor layer, a junction interface between the first semiconductor layer and the second semiconductor layer being {001} or {111} plane, and a two-dimensional carrier gas being generated in the heterojunction interface.

Abstract: The present invention relates to electronic devices formed in crystallites of III-V nitride materials. Specifically, the present invention simplifies the processing technology required for the fabrication of high-performance electronic devices in III-V nitride materials.

Abstract: A method for forming a multi-level conductive structure on an integrated circuit. The method includes forming a first conductive layer 108 and forming a first dielectric layer 112 above the first conductive layer. The method further includes forming a second conductive layer 302 above the first dielectric layer. There is also included etching through the second conductive layer and at least partially into the first dielectric layer to form a trench 706 in the second conductive layer and the first dielectric layer, thereby removing at least a portion of the dielectric layer and forming a first conductive line 503 and a second conductive line 505 in the second conductive layer. Further, the method includes depositing a low capacitance material 908 into the trench. The low capacitance material represents a material having a dielectric constant lower than a dielectric constant of the first dielectric layer.

Abstract: A semiconductor device includes multilayer film carriers, a plurality of connection layers having innerleads protruded from the film carriers, and a semiconductor chip having electrode pads connected to the innerleads.

Abstract: An integrated electronic device having an electric connection between a first electrode of a semiconductor chip and a second electrode of a circuit board. One embodiment according to the present invention is a method for fabricating an integrated electronic device having an electric connection between a first electrode of a semiconductor chip and a second electrode of a circuit board, both surfaces of the first and second electrodes having an adhesive tendency to molten metal, the method comprising the steps of forming a metal bump on the first electrode, the metal bump being made of a soldering metal alloy consisting of a solid phase component and a liquid phase component at an operating temperature; and forming an electric connection between the first electrode and the second electrode by heating the soldering metal alloy so as to adhere to the surface of the second electrode.

Abstract: A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the art. Such die may be employed in singulated fashion on a carrier substrate as an alternative to so-called "flip chip" die, or in vertically-stacked fashion to form a sealed multi-chip module the same size as the die from which it is formed. Certain vias of the various dice in the stack may be vertically aligned or superimposed to provide common access from each die level to a terminal such as a bond pad or C4 or other connection on the back side of the lowermost die contacting the carrier, while other stacked vias are employed for individual access from each die level to the carrier through the back side of the lowermost die.

Abstract: A technique is disclosed for general IC structures to modify the layout of electrically unisolated metal lines before patterning same so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer. Upon such standardization of metal line spacing, the intermetal dielectric will be planarized in a single process step of deposition. Circuit layout design modifications can be made by adding electrically isolated dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing between the metal lines and dummy metal features. As the nonstandard spacing between metal lines becomes standardized, an intermetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.

Abstract: A method of mounting a semiconductor device first forms a barrier layer on one surface of an semiconductor substrate made of Si. Then, a first Au layer is formed on the barrier layer. Accordingly, a semiconductor device is provided. The barrier layer is formed of metal for preventing mutual diffusion of Si in the Si semiconductor substrate with Au in the first Au layer at a high temperature of 600.degree. C. or higher. A step of acquiring a package substrate forms a metal coated layer on a base first and then forms a second Au layer on the surface of the metal coated layer. Then, the semiconductor device is placed on the package substrate with the first and second Au layers contacting with each other, and the semiconductor device and the package substrate are scrubbed against each other. Consequently, the first and second Au layers form Au--Au eutectic layer, thereby connect the semiconductor device to the package substrate.

Abstract: A semiconductor package having positioned therein a protection layer which protects the integrated circuit chip from electrostatic discharge (ESD) damage. The protection layer is made of a material that has at steady state a high electrical resistance, but when a high ESD potential is applied to it, it becomes highly conductive. A preferred material is SurgX.TM., which is a polymer. The layer is positioned to shunt the potential away from the chip, and can be positioned operatively between a signal lead and a power plane or between different signal leads. That is, the protection layer can be sandwiched between the lead and the conductive member, or the lead can be within the layer. Another preferred construction incorporates the protection material in a tape construction as a thin layer sandwiched between and bonded to a layer of leads and a ground plane.

Abstract: A packaged semiconductor device includes an LSI chip, a chip size package integrally bonded to the LSI chip to mount and hold the LSI chip thereon in order to connect an electrode of a board on which the LSI chip is to be mounted and an electrode of the LSI chip to each other, an electrode formed on a surface of the package opposite to a surface thereof which is bonded to the LSI chip, so as to be connected to the electrode of the board, at least one through hole formed to extend through the LSI chip and the package, and a connecting conductor formed to extend through the through hole in order to connect the electrode of the package and the electrode of the LSI package to each other.

Abstract: A fabrication method for a semiconductor device is provided, which is able to increase pattern-to-pattern lithography overlay accuracy. After a first layer made of a first material is formed, first and second slits serving as a first alignment mark are formed in the first layer. The first and second slits are spaced with a specific distance and are approximately parallel to each other. Each of the first and second slits is filled with a second material. Then, a second layer made of a third material is formed on the first layer. Subsequently, a mask is formed on the second layer. The mask has a first pattern serving as a second alignment mark. The second alignment mark is overlapped with the first and second slits serving as the first alignment mark. Preferably, the first alignment mark provides the main scale of a caliper, and the second alignment mark provides the vernier scale of the caliper.