Abstract: A process for producing laminated film/metal structures comprising bumped circuit traces on a non-conductive substrate wherein a copper sheet/polyimide film laminate is coated with resist on the exterior surfaces. The resist adjacent the polyimide film is selectively exposed and etched to expose an area of the polyimide film. The exposed polyimide film is etched to form vias through the polyimide film to the inner side of the copper sheet. The resist adjacent the polyimide film is stripped away and a metal bump is electrolytically plated through each via onto the copper sheet. A subsequent layer of resist is electrophoretically applied over the bumps. The resist material adjacent the copper sheet is then selectively exposed and etched to expose areas of the copper sheet. The exposed copper sheet is etched to form circuit traces and the remaining resist adjacent both the polyimide film and the copper sheet is stripped away.

Abstract: A power semiconductor module in which a plurality of power semiconductor elements forming a bridge circuit are provided together with control circuits. The module includes a common casing which accommodates a metal base, a main circuit section, and a control circuit section. The main circuit section has a plurality of semiconductor elements of the bridge circuit mounted on a ceramic insulating board which is thermally coupled to the metal base. The main circuit section also supports connecting conductors to which the semiconductor elements are connected. In the control circuit section are mounted control circuits for the semiconductor elements. The control circuits are mounted on a wiring substrate which is formed by wiring conductors on an insulating board. The main circuit section is connected through a bond to the control circuit section. Input and output terminals of the bridge circuit are extended from the connecting conductors of the main circuit section.

Abstract: An electronic device (10) such as that of the micromechanical type having a time-released source of a passivant (20). This source (20) is preferably comprised of an impregnated molecular sieve/binder combination, preferably being a polymer. The passivant may be PFDA. The time-released passivant source continuously over the life of the device reduces any tendency of engaged or contacting elements to stick, adhere, or otherwise resist separation. The present invention finds particular use in spatial light modulators of the DMD type. The molecular sieve/binder can also include getter/desiccant source, such as a non-evaporable getter to remove moisture from the hermetically sealed electronic device.

Abstract: A package for surface acoustical wave (SAW) device includes an electrically insulative substrate having a first surface with an electrically conductive layer formed thereon. A first surface of the SAW device is attached to the electrically conductive layer. An electrically conductive adhesive bead overlies the substrate first surface and surrounds the SAW device. An electrically conductive lid defines a free space over a second surface of the SAW device, the lid being electrically connected to the electrically conductive layer by the adhesive bead and one or more tabs extending from the lid through the adhesive bead to the electrically conductive layer. The electrically conductive adhesive bead, electrically conductive layer and electrically conductive lid enclose and shield the SAW device.

Abstract: A semiconductor device package is equipped with devices for preventing the formulation of air traps in its encapsulated package body. These devices include dummy block leads formed on the outermost inner lead of each row of inner leads, and extended portions formed on each tie bar. Each dummy block lead extends from the end of an outermost inner lead and is integrally formed therewith. The tie bar extended portions are separated into several parts defined by spaces between the parts, and the several parts are formed integral with each other and with the tie bar. The dummy block leads and the tie bar extended portions may be formed so as to be inclined relative to horizontal and with jagged edges at their side surfaces. The dummy block leads and tie bar extended portions serve to reduce the velocity of the potting resin which forms the encapsulate, as it enters the die cavity for encapsulation, but before the resin actually contacts the chip or the inner leads.

Abstract: A field effect transistor having an excellent transfer conductance and an improved gate leakage current and breakdown voltage is provided. In the transistor, a multiquantum barrier structure 4 is arranged between a gate and a channel layer 3 along a channel layer 3 and having an effect of reflecting incident overflowing carriers a s waves in with with phase conditions of total reflection allowing mutual enhancement of the incident and reflected wave in a region between a channel layer 3 and a gate electrode 10 and/or in a region opposite to the gate electrode 10 relative to the channel layer 3.

Abstract: A leadframe (100) has a flag having an outer contour that tapers from first and second opposing ends (160, 162) to a common point, the midline (200) of the flag. The tapering of the leadframe is continuous, extending from points adjacent the first and second ends or from the ends themselves, to the common midline. According to this structure, a wide range of die sizes may be accommodated with a single leadframe, while simultaneously preventing popcorning of the packaged semiconductor device (300) incorporating the leadframe.

Abstract: A carrier element in card form has at least one integrated semiconductor circuit disposed on the carrier element. External terminals of the data carrier card have a terminal surface disposed on an edge surface of the carrier element. Further terminal surfaces are preferably provided on main surface areas of the carrier element for an external terminal. If a plurality of data carrier cards are laid congruently one on top of the other, an electrical connection between the external terminals of the respective data carrier cards is established in a simple way.

Abstract: A semiconductor device comprising a low-heat-resistance heat discharging route suitable for small semiconductor devices, such as an IC card, is disclosed. Heat arising from electronic parts is efficiently dispersed to the outside, thereby accomplishing a decrease in size and a heightening of function. In a specific embodiment, a CPU is mounted on a substrate in a position of thermal via holes. A high-heat-conducting material such as semifluid silicone rubber is placed between a CPU mounting face of the substrate and lower panel located on the opposite side of the substrate. The high-heat-conducting material is a filler having the ability to change shape and the property of electrical nonconductivity. A greater part of the heat arising from the CPU is transmitted through the thermal via holes from the CPU mounting face of the substrate to the opposite side, and further to the high-heat-conducting material which conveys the heat to the lower panel.

Abstract: A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

Abstract: A semiconductor package, which secures the protection of circuit elements from the external environment, is disclosed. A single in-line package (SIP) is constructed by fixingly sealing a hybrid integrated circuit component within a casing with epoxy resin. A sleeve is bonded on the surface of a ceramic substrate. The sleeve is formed with silicon rubber into a pocket shape so as to cover respective circuit elements of the hybrid integrated circuit component. In the sleeve is made an opening part. Silicon gel is poured into the sleeve as a fixingly sealing material and cured to seal the respective circuit elements. Terminals downwardly extends in parallel with each other from an end part of the ceramic substrate through an opening part of the casing.

Abstract: A multi-chip module that incorporates multiple flip chip (16) mounted on a daughter board (12), which in turn is flip-chip mounted onto a product mother board (10). The daughter board (12) is preferably a silicon substrate having solder bump terminals (14) and at least one conductor pattern on a surface thereof. The surface of the daughter board (12) may also have conductive runners and any passive electronic components required by the module. Mounted to the conductor pattern of the daughter board (12) are the flip chips (16) having solder bump terminals (18) that are registered and soldered to the conductor pattern of the daughter board (12). The solder bump terminals (14) of the daughter board (12) are then registered and soldered to a complementary conductor pattern on the mother board (10), such that the flip chips (16) are disposed between the daughter board (12) and the mother board (10).

Abstract: A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.

Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

Abstract: The specification describes a thermocompression bonding process using anisotropic conductive film (ACF) bonding material in which the bonding pads are shaped to prevent depletion of conductive particles in the bonding region during compression. The process is useful in bump technology for interconnecting component assemblies on substrates such as glass, printed wiring boards, etc. The shaped structure can be made using photodefinable polymer strips around the bonding pads where the strips are thicker than the bonding pad. Alternative approaches to shaping one or both of the mating conductive surfaces are disclosed.

Abstract: A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.

Abstract: A microelectronic assembly (10) includes an integrated circuit die (12) mounted onto a substrate (14) by solder bump interconnections (32). The die (12) and the substrate (14) are spaced apart by a gap (30) that is filled with a polymeric encapsulant (16). The die (12) includes a die perimeter (24) and a face (27) facing away from the substrate (14). A polymeric reinforcement (18) is disposed onto the die face (27) to protect the die (12) and to reduce the effects of thermally induced stresses on the die (12) and the solder bump interconnections (32). The polymeric reinforcement (18) is spaced apart from the die perimeter (24) to maintain a desired peripheral fillet geometry of the encapsulant (16).

Abstract: An adapter is described herein which releasably connects a ball grid array package to a printed circuit board, or to a testing board, such that the ball grid array package may be reused. In a preferred embodiment, an inexpensive base of the adapter contains solder balls or terminals on its bottom surface in the same pattern as the solder balls on the bottom of the ball grid array package. The terminals protrude slightly through the top surface of the base. A conductive elastomer, which conducts in one direction only, is then placed over the top surface of the base of the adapter so as to make electrical contact with the protruding terminals on the base. A ball grid array package is then placed over the conductive elastomer such that the solder balls on the bottom surface of the ball grid array package electrically contact respective terminals on the base.

Abstract: A three-dimensional semiconductor circuit assembly wherein each of several circuit chips is provided with patterned metal layers that extend from the circuit surface onto an edge side of the chip, then the chips are adhesively bonded to opposite surfaces of one or more dielectric spacers, respectively, whereby the edge sides of the resulting multiple-chip stack are readily connected to metal patterns on a substrate.

Abstract: A semiconductor device including an insulation film superior in both planarization and water resistance is obtained. In this semiconductor device, a first insulation film including impurities is formed on a conductive layer. A film is formed between the first insulation film and the conductive layer for substantially preventing impurities from entering the conductive layer. Water resistance of the first insulation film is improved since impurities are included in the first insulation film. By using an insulation film superior in planarization as the first insulation film, a first insulation film superior in both planarization and water resistance can be obtained. The film provided between the first insulation film and the conductive layer prevents the impurities of the first insulation film from entering the conductive layer. Therefore, reduction in the reliability of the conductive layer can be prevented.