Abstract: A method of forming an optoelectronic semiconductor device involves providing an amorphous substrate. A transparent and conductive oxide layer is deposited on the amorphous substrate. The transparent and conductive oxide layer is annealed to form an annealed transparent and conductive oxide layer having a cubic-oriented and/or rhombohedral-oriented surface. A nanorod array is formed on the cubic-oriented and/or rhombohedral-oriented surface of the annealed transparent and conductive oxide layer. The annealing of the transparent conductive oxide layer and the formation of the nanorod array are performed using molecular beam epitaxy (MBE). The nanorods of the nanorod array comprise a group-III material and are non-polar.

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a substrate and an array layer disposed on a side of the substrate; a light-emitting layer, where the light-emitting layer is on a side of the array layer away from the substrate and includes a plurality of light-emitting units; and a color filter layer. The color filter layer includes a light-blocking portion and a plurality of color resist units; the plurality of color resist units is disposed corresponding to the plurality of light-emitting units; at least two color resist units of a same color have different orthographic projection shapes on a same first plane; a first plane at least includes one of a first sub-plane and a second sub-plane; the first sub-plane is a plane perpendicular to the substrate; and the second sub-plane is a plane in parallel with the substrate.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: A high-voltage switch, whose operation leverages the speed of electrons to generate the “on” time of the pulse in combination with the speed of light to generate the “off” time of the pulse, is described. In one example, the high-voltage switch includes a first electrode, a second electrode spaced apart from the first electrode, a region of non-absorbing material occupying a portion of the space between the first and second electrodes and allowing a laser pulse to propagate therethrough without substantial absorption, and a region of absorbing material occupying another portion of the space and producing a charged particle cloud upon receiving the laser pulse. The high-voltage switch remains “on” upon the charged particle cloud reaching an electrode and until it has been collected by the electrode, and where the high-voltage switch remains “off” subsequent to the collection and until another generated charged particle cloud reaches the electrode.

Abstract: A cell of fluidic assembly of microchips on a substrate, including: a base having its upper surface intended to receive the substrate; a body laterally delimiting a fluidic chamber above the substrate; and a cover closing the fluidic chamber from its upper surface, wherein the body comprises first and second nozzles respectively emerging onto opposite first and second lateral edges of the fluidic chamber, each of the first and second nozzles being adapted to injecting and/or sucking in a liquid suspension of microchips into and/or from the fluidic chamber, in a direction parallel to the mean plane of the substrate.

Abstract: A display device includes a metal layer, a boots layer, a passivation layer, and a conductive layer. The boots layer is located below the metal layer. The boots layer is partially overlapped with the metal layer. The passivation layer covers the metal layer and the boots layer. The conductive layer covers the passivation layer and the metal layer. The conductive layer is overlapped with the boots layer along a direction of the orthogonal projection.

Abstract: An elliptically polarizing plate and an organic light-emitting device. The elliptically polarizing plate has superior visibility and excellent reflection characteristics and color characteristics on the side as well as the front, and an organic light-emitting device comprising the same.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

Abstract: A display device and method of manufacturing same includes: a display panel having a pixel area and a peripheral area adjacent to the pixel area, a light control layer disposed on the display panel and at least partially overlapping the pixel area, a light blocking portion at least partially overlapping the peripheral area, and a protective layer disposed between the light control layer and the light blocking portion.

Abstract: An embodiment of the present invention provides an optical film (10) including a light-transmitting base material (11), a hard coat layer (12), and an inorganic layer (13) in this order, wherein the hard coat layer (12) is in contact with the inorganic layer (13), the hard coat layer (12) contains a binder resin (12A) and inorganic particles (12B), the hard coat layer (12) has a film thickness of 1 ?m or more, and the hard coat layer (12) has an indentation hardness of 200 MPa or more.

Abstract: The present application discloses an organic light-emitting display and a manufacturing method thereof. The organic light-emitting display includes a display panel, and the display panel includes a substrate layer, an organic light-emitting layer, a thin film encapsulation layer, and a thin film encapsulation layer, and an antenna disposed on an upper surface of the thin film encapsulation layer stacked sequentially from bottom to top. The size and position of the antenna are more flexible in design, and the antenna is directly placed on the thin film encapsulation layer, which dodges light-emitting pixels in the light-emitting layer, thereby avoiding the occurrence of Moire.

Abstract: Provided are a flexible display substrate, a display panel, a display device, and a manufacturing method, relating to the technical field of display. The flexible display substrate is provided with a first bonding and a second bonding region. The first bonding region and the second bonding region are configured to be bonded to an electronic component, and a thickness of the flexible display substrate in the first bonding region is greater than a thickness of the flexible display substrate in the second bonding region in a direction perpendicular to the flexible display substrate.

Abstract: A display apparatus includes a substrate on which a central area having a display area and a peripheral area disposed around the central area are defined. The display apparatus includes a display area inorganic layer on the display area and extending to a portion of the peripheral area; and an encapsulation inorganic layer covering the display area, on the display area inorganic layer, and having an edge that is in parallel with or extending over an edge of the display area inorganic layer.

Abstract: A display device includes a display substrate including a plurality of pixels and including an active area longer than a display region, and a frame region formed to surround the active area, and a cover glass attached to a display surface side of the display substrate. A frame is provided in a periphery of the cover glass, and the frame covers an outer periphery of the active area. The display region is a region where the active area and a region surrounded by the frame of the cover glass overlap each other.

Abstract: A microcavity pixel design and structure allowing for tuning the optical cavity length of the microcavity of a microcavity pixel structure. This is achieved by including an intermediate electrode in the device which has an overhang region to form a connecting area to a bottom electrode, alleviating design restrictions in material type and dimensions throughout the optical microcavity tuning process. A method for the fabrication of a multi-colored microcavity pixel array facilitating the use of blanket deposition methods for select layers within a microcavity pixel structure.

Abstract: Disclosed is an organic light-emitting device including an emission layer that includes a compound satisfying conditions 5? and 6 below: 0 eV<?EST2?0.1 eV??Condition 1: ?EST>0.

Abstract: A display device includes: a first base having a display area; light-emitting elements on the first base; and an encapsulation layer over the light-emitting elements. The encapsulation layer includes: a first inorganic layer; an organic layer on the first inorganic layer; and a second inorganic layer on the organic layer. The first inorganic layer includes: a first buffer layer on the light-emitting elements; a first barrier layer on the first buffer layer; a first porous layer on the first barrier layer; a second barrier layer on the first porous layer; and a second buffer layer on the second barrier layer. A refractive index of the first buffer layer, the first barrier layer, and the first porous layer are different from one another, and the refractive index of the first porous layer is smaller than the refractive index of the first buffer layer and the first barrier layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.