Abstract: Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execution are identified. The code unit that includes those triggering read operations is modified so that the code unit branches to a prefetch predictor. The prefetch predictor observes sequence patterns of data sources of triggering read operations and develops prefetch predictions based on the observed data source sequence patterns. After a prefetch prediction gains reliability, the prefetch predictor supplies a predicted data source to a prefetcher coincident with triggering of runahead execution.

Abstract: Methods and apparatuses for providing a data storage system having snapshot restore capabilities are provided. In particular, snapshots may be taken to represent a state of a storage volume at different times. The state of the storage volume may be returned to the state represented by any snapshot even while the storage volume continues to accept read and write operations. Furthermore, these features are provided in the context of a sparse snapshot structure, according to which multiple copies of individual data chunks are not maintained by the data storage system.

Abstract: A multiple-location read, single-location write operation is implemented using transient blocking synchronization support. The multiple-location read, single-location write operation involves first acquiring transient ownership of a memory location to be modified and then acquiring transient ownership of at least one other memory location, the contents of which are read and used to modify the memory location first acquired.

Abstract: A wear-leveling method for managing flash memory is provided, including an access process to consult a translation table when accessing a data block in the data region, and a reconstruction process to reconstruct the translation table when powering on the flash memory. The translation table is defined to include a plurality of entries, and each entry includes a physical address field and an enduring counter field. The logical address of a data block is used as input to map to the entry in the translation table. The access process, further including a read process and an erase/program process, maps the logical address to the physical address, and uses the enduring counter to determine whether an update is required to avoid the disturbance. The reconstruct process uses the information stored in the spare data region to reconstruct the translation table for the access process to consult during flash memory accesses.

Abstract: This invention is a system and method for determining configuration or simulating performance of one or more data storage systems. This invention may be used in many useful ways including for configuring or modeling a data storage environment, problem isolation, and general design.

Abstract: Provided are a method, system, and article of manufacture, wherein a first storage unit is coupled to a second storage unit. The first storage unit and the second storage unit are detected. A determination is made that the first storage unit is capable of responding to a write operation faster than the second storage unit, and that the second storage unit is capable of responding to a read operation at least as fast as the first storage unit. Data is written to the first storage unit. A transfer of the data is initiated from the first storage unit to the second storage unit. The data is read from the second storage unit, in response to a read request directed at both the first and the second storage units.

Abstract: Relatively-temporary applications may be installed. As a result of the installation and/or execution of such an application, an associated application isolated storage unit may be established. When established, the application isolated storage unit is designated for private storage use by the associated application. Additionally, a linkage between the application isolated storage unit and the associated application is created. Upon initiation of a reclamation procedure, the linkage from the application isolated storage unit is traced to the indicated location of the associated application. If the associated application no longer exists, the application isolated storage unit is deleted so as to reclaim the memory space.

Abstract: Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests are presented to memory may be changed to avoid or minimize page replace conflicts, DIMM turn around conflicts, and other types of conflicts that could otherwise impair the efficiency of memory operations.

Abstract: Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

Abstract: A content addressable memory (CAM) device having a range compare function. A boundary value is stored within a plurality of CAM cells within the CAM device. A range compare operation is performed to determine whether a comparand is greater than the boundary value. A result signal is asserted if the comparand is greater than the boundary value.

Abstract: Transactions are granted concurrent access to a data item through the use of an optimistic concurrency algorithm. Each transaction gets its own instance of the data item, such as in a cache or in an entity bean, such that it is not necessary to lock the data. The instances can come from the data or from other instances. When a transaction updates the data item, the optimistic concurrency algorithm ensures that the other instances are notified that the data item has been changed and that it is necessary to read a new instance, from the database or from an updated instance. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.

Abstract: A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a value within a second range. A detector circuit detects whether or not the value from the primary circuit is within the desired output range for the random number generator circuit, and selects either the value from the primary circuit or the value from the secondary circuit in response. The second range is the desired output range and the first range encompasses the second range. In one embodiment, the primary circuit has complex harmonics but may generate values outside the desired range. The secondary circuit may have less complex harmonics, but may generate values only within the desired range. In one implementation, the random number generator circuit is used to generate a replacement way for a cache.

Abstract: An architecture, method, and apparatus for managing a data buffer (Data Buffer Management DBM). A data buffer within the DBM is an unified linear memory space, and is divided into numbered physical pages with a predetermined page size. A memory map translates logical address spaces for storing/reading DBM transferred data to the physical address spaces. Each packet to be written into DBM is assigned a frame number or frame handler; thereafter, that frame number will be passed by the original owner (a device attached to the data buffer) to different processes for reading out and/or modifying the associated packet or packet data. Frame number assignment is done prior to actual data transfer by request of the data owner. The frame number request is done prior to moving data from the owner's local memory into the DBM's data buffer. Frame number is allocated dynamically by the DBM.

Abstract: Memory and processing required for managing virtual memory segments is reduced by overloading the existing page table entries in a virtual memory page table to encode virtual memory segmentation data. Therefore, no additional data structures are required for virtual memory segment management. Virtual memory segmentation information is stored in the actual page table entries, using bits that are reserved as unused for the given computer architecture to identify the virtual memory segment management information.

Abstract: The caching of heterogeneous bean sets has been improved from requiring each bean to have its own cache instance to caching the beans in a single cache. The beans can be identified by generating a unique identifier that is a combination of the bean's primary key and a self-reference identifier of the bean manager associated with that bean. The average size of a bean set associated with a bean manager can be specified such that the cache allocates memory for that set based on the average size. A callback interface can also be used to shift knowledge of a bean life cycle back to the bean manager. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.

Abstract: Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.

Abstract: A method to export and then import a logical volume with assigned storage attributes, from a first information storage medium to a second information storage medium. The method maintains a logical volume in a first information storage medium. The method assigns one or more first storage attributes to that logical volume. The method further includes forming an import list logical volume. The method further includes defining a plurality second storage attributes. The method further includes importing the logical volume, and the assigned first storage attributes, into a second information storage medium. The method then determines if the import list logical volume specifies use of one or more second storage attributes. If the import list logical volume specifies use of one or more second storage attributes, then the method assigns to the logical volume those one or more second storage attributes.

Abstract: A virtual mode virtual memory manager method and apparatus are provided. Mechanisms are provided for allowing a virtual memory manager to operate in virtual mode utilizing virtual addresses for all of its own data structures, allowing for physical discontinuity of the physical memory backing those data structures. First order virtual memory manager metadata is included for resolving system wide virtual memory page faults. Second order virtual memory manager metadata is provided to resolve faults on the first order virtual memory manager metadata. The second order virtual memory manager metadata is associated with pinned entries in a page table and thus, faults on the second order virtual memory manager metadata cannot occur.

Abstract: Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Abstract: The storage regions under command of a storage controller can be simply enabled and disabled to access to by automatically registering connected host computers. Such system can be achieved by taking a step of acquiring N—Port—Name information included in a login frame from the host computers, and a step of displaying a table of access right of host computers to a logical unit under command of storage controller. A security table for the storage controller can be generated by supervisor's setting the access enable/disable flag information.