Abstract: This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A method, apparatus, and computer instructions for managing memory blocks. In response to a request to deallocate a memory block from a partition, all processes are prevented from using the memory block. The memory block is isolated from the partition in response to preventing use of the memory block. The memory block is deallocated to form a free memory block.

Abstract: Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

Abstract: A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination of a bus arbiter and a switch arbiter, or elsewhere. The system also includes cache control circuitry capable of using the source tag to make cacheability decisions. The cache control circuitry, and therefore the cacheability decisions, could be fixed—e.g., by a user—or could be alterable based on a suitable algorithm—similar, e.g., to a least-recently-used algorithm—that monitors cache usage and memory requests. The caching system is particularly useful where the cache being controlled is large enough to cache the results of I/O and similar requests and the requesting resources are I/O or similar resources outside the core logic chipset of the computer system.

Abstract: A cache memory comprises a group of cache pages which are normal data areas, and a group of work pages each for saving DIRTY data in an associated cache page. When write data transferred from a host computer is written into said cache memory, a host interface controller saves data in a portion in which a write range overlaps a DIRTY range into a work page, and retrieves the data saved in the work page to an associated cache page when a transfer of the write data is interrupted. A disk interface controller writes back the DIRTY data on said cache memory.

Abstract: A data reader includes: a memory card interface communicating with a memory card in which is recorded data such as video, the recorded date of that data, and a reproduction time limit of that data; a real time clock detecting the current date; a display unit reading out data from the memory card to display video or the like; and a CPU comparing the current date detected by the real time clock with the recorded date and reproduction time limit of the data recorded in the memory card to determine whether reproduction of the data recorded in the memory card is allowed or not.

Abstract: A storage system has a host computer and a storage control device connected thereto. The system controls duplication of data in a first logical volume to be stored in real-time in a second logical volume different therefrom, and makes a logical volume identifier and a data set identifier for the first volume described in the first volume's management information and a logical volume identifier and a data set identifier for the second volume described in the second volume's management information match during the duplication. The system generates a control program for setting the first volume's logical volume identifier and data set identifier in the first volume's management information and the second volume's logical volume identifier and data set identifier in the second volume's management information to differ and, by executing this program, makes the second volume be recognized by an OS as a volume independent of the first volume.

Abstract: When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true. The result of logical sum is used as matched data logical-OR information. In a primary searching operation, the associative memory (1) is supplied with the search data (12) to provide the matched data logical-OR information on matched data logical-OR lines. Then, the associative memory (1) carries out a secondary searching operation supplied as search data with the matched data logical-OR information obtained by all of storage data coincident upon the primary searching operation. Only a match line (5) coincident with the matched data logical-OR information is selected as the secondary search result. The associative memory is used in a network router to calculate an optimum memory address signal (403) by encoding the selected match line (5).

Abstract: A software monitor, interposed between the hardware layer of a computer system and one or more guest operating systems, constructs and maintains a guest-physical-address-to-host-physical-address map for each guest operating system, and maintains a virtual memory addressing context for each guest operating system that may include a virtual-hash-page table for each guest operating system, the contents of translation registers for each guest operating system, CPU-specific virtual-memory translations for each guest operating system, and the contents of various status registers.

Abstract: Methods and an apparatus for RAID load balancing are provided. One exemplary method includes establishing first and second counters where the first counter is associated with a first drive and the second counter is associated with a second drive. Next, a command is received form an operating system. Then, it is determined if the received command is a read command. If the received command is a read command, then the counters are examined to determine which of the counters is a lower value counter or if the counters are of equal value. Next, a drive associated with the lower value counter is selected or if the counters are of equal value a first drive is selected. The lower value counter is then incremented. Then, the read command is directed to the drive associated with the lower value counter or the first drive if the counters are of equal value.

Abstract: A data storage apparatus that stores data series provided from an exterior system in a recording medium using a buffer memory to reduce the processing time of the data storage. The data series are temporarily stored in the buffer memory separately. If a group of the data series is determined to make a series of data as a whole, the group of the data series is combined, and transferred to the recording medium at one time in order to reduce seek time and rotation wait time from those that would be required if the group of the data series is transferred to the recording medium separately.

Abstract: The present invention relates to a data processing system comprising a processor (100), at least one data memory (132), at least one program memory (134) and a main bus (110), common to the data and program memories and connecting these memories to the processor, characterized in that at least one of the memories has a rapid-access mode and in that the device also comprises a distribution interface (120) between the main bus (110) and the memories in order to alternately put in communication, by means of the main bus, one from among the data memory and the program memory with the processor, in a so-called active-access mode, and to keep the other memory in a so-called passive-access mode allowing subsequent rapid access.

Abstract: In a first aspect, a method is provided for updating a compressed cache. The method includes the steps of (1) initiating an update routine for replacing first data stored within the cache with second data, wherein a first section of a compressed data band stored in the cache includes the first data and a second section of the compressed data band includes third data; and (2) in response to initiating the update routine, replacing the first data within the compressed data band with the second data without decompressing the third data. Numerous other aspects are provided.

Abstract: A method of transferring data in a processing system comprising a shared memory for storing data blocks, a plurality of processors, at least one of the processors having a cache memory for the data blocks, a plurality of data buses to each one at least one processor is connected, cross-bar for selectively connecting the data buses and the shared memory therebetween; the method comprises the steps of requesting the reading of a data block from the shared memory by a requesting processor, if the requested data block is present in modified form in the cache memory of an intervening processor, requesting an access to the corresponding data bus by the intervening processor, granting the access to the intervening processor, and to any other data bus available to the cross-bar, and sending the modified data block onto the data bus corresponding to the intervening processor and then onto the other data buses available.

Abstract: In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

Abstract: The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like distributed among a plurality of sites according to user demand for these storage resources. Specific embodiments provide users the capability to bring new resources on line, define pathways between resources, and the like. Embodiments can obviate the need for system programmers to manually configure storage resources at a user's site.

Abstract: One embodiment of the present invention provides a system for synchronizing a cache in a computer system through a peer-to-peer refreshing operation. During operation, the system determines the age of an entry in the cache. If the age of the entry exceeds a life span for the entry, the system invalidates the entry in the cache. The system subsequently refreshes the entry by retrieving an updated version of the entry from a peer of the computer system, if possible, instead of from a centralized source for the entry.