Patents Examined by Nilufa Rahim
  • Patent number: 11664425
    Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: May 30, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
  • Patent number: 11664329
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 30, 2023
    Assignee: Google LLC
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Patent number: 11658232
    Abstract: A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 23, 2023
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Tian-Fu Zhang, Li-Hui Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 11658118
    Abstract: A semiconductor device includes a first gate line and a second gate line extending along a first direction, a third gate line extending along a second direction and between and directly contacting the first gate line and the second gate line, a drain region adjacent to one side of the third gate line, a fourth gate line extending along the second direction and between and directly contacting the first gate line and the second gate line, and a first metal interconnection extending along the second direction between the third gate line and the fourth gate line. Preferably, the third gate line includes a first protrusion and the fourth gate line includes a second protrusion.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: May 23, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 11637138
    Abstract: A pixel circuit includes a trench etched into a front side surface of a semiconductor substrate. The trench includes a bottom surface etched along a <100> crystalline plane and a tilted side surface etched along a <111> crystalline plane that extends between the bottom surface and the front side surface. A floating diffusion is disposed in the semiconductor substrate beneath the bottom surface of the trench. A photodiode is disposed in the semiconductor substrate beneath the tilted side surface of the trench and is separated from the floating diffusion. The photodiode is configured to photogenerate image charge in response to incident light. A tilted transfer gate is disposed over at least a portion of the bottom surface and at least a portion of the tilted side surface of the trench. The tilted transfer gate is configured to transfer the image charge from the photodiode to the floating diffusion.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 25, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventor: Qin Wang
  • Patent number: 11631802
    Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 18, 2023
    Assignee: Headway Technologies, Inc.
    Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
  • Patent number: 11631667
    Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, where the via includes tungsten, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: April 18, 2023
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11626524
    Abstract: A photoexcitable material includes: a solid solution of MN (where M is at least one of gallium, aluminum and indium) and ZnO, wherein the photoexcitable material includes 30 to 70 mol % ZnO and has a band gap energy of 2.20 eV or less.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: April 11, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Hideyuki Amada, Fumiaki Kumasaka, Toshio Manabe, Toshihisa Anazawa, Yoshihiko Imanaka
  • Patent number: 11621354
    Abstract: Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Stephanie Bojarski, Babita Dhayal, Biswajeet Guha, Tahir Ghani
  • Patent number: 11618675
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 4, 2023
    Assignee: SiTime Corporation
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Patent number: 11621267
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 11621290
    Abstract: A solid-state imaging element includes a pixel including a first imaging element, a second imaging element, a third imaging element, and an on-chip micro lens 90. The first imaging element includes a first electrode 11, a third electrode 12, and a second electrode 16. The pixel further includes a third electrode control line VOA connected to the third electrode 12 and a plurality of control lines 62B connected to various transistors included in the second and third imaging elements and different from the third electrode control line VOA. In the pixel, a distance between the center of the on-chip micro lens 90 included in the pixel and any one of the plurality of control lines 62B included in the pixel is shorter than a distance between the center of the on-chip micro lens 90 included in the pixel and the third electrode control line VOA included in the pixel.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: April 4, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Nobuhiro Kawai, Hideaki Togashi, Fumihiko Koga, Tetsuji Yamaguchi, Shintarou Hirata, Taiichiro Watanabe, Yoshihiro Ando
  • Patent number: 11616131
    Abstract: A semiconductor device includes an active region spanning along a first direction. The semiconductor device includes a first elongated gate spanning along a second direction substantially perpendicular to the first direction. The first elongated gate includes a first portion that is disposed over the active region and a second portion that is not disposed over the active region. The first portion and the second portion include different materials. The semiconductor device includes a second elongated gate spanning along the second direction and separated from the first elongated gate in the first direction. The second elongated gate includes a third portion that is disposed over the active region and a fourth portion that is not disposed over the active region. The third portion and the fourth portion include different materials.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Jier Yang, Tai-Hsin Chiu
  • Patent number: 11611057
    Abstract: A display device includes a window, an anti-reflector disposed under the window, the anti-reflector including: a first area having a first transmittance; and a second area having a second transmittance higher than the first transmittance, and a display panel disposed under the anti-reflector, the display panel including: a first display area having a first resolution; and a second display area having a second resolution lower than the first resolution. The second area overlaps with the second display area in a plan view.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 21, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jinwoo Park, Wonkyu Kwak, Dongwook Kim, Hyun-Chol Bang
  • Patent number: 11605650
    Abstract: A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 14, 2023
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Sung Joo Lee, Jeong Ho Cho, Jae Ho Jeon, Hyeon Je Son, Hae Ju Choi, Min Je Kim
  • Patent number: 11587825
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 21, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Patent number: 11581504
    Abstract: An electroluminescent device comprising a first electrode and a second electrode facing each other, an emission layer disposed between the first electrode and the second electrode and including at least two light emitting particles, a hole transport layer disposed between the first electrode and the emission layer, and an electron transport layer disposed between the emission layer and the second electrode, wherein the electron transport layer comprises an inorganic layer disposed on the emission layer, the inorganic layer comprising a plurality of inorganic nanoparticles; and an organic layer directly disposed on at least a portion of the inorganic layer on a side opposite the emission layer, wherein a work function of the organic layer is greater than a work function of the inorganic layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Ho Kim, Sung Woo Kim, Eun Joo Jang, Dae Young Chung
  • Patent number: 11579033
    Abstract: The present invention provides a MEMS pressure sensor and a manufacturing method. The pressure is formed by a top cap wafer, a MEMS wafer and a bottom cap wafer. The MEMS wafer comprises a frame and a membrane, the frame defining a cavity. The membrane is suspended by the frame over the cavity. The bottom cap wafer closes the cavity. The top cap wafer has a recess defining with the membrane a capacitance gap. The top cap wafer comprises a top cap electrode located over the membrane and forming, together with the membrane, a capacitor to detect a deflection of the membrane. Electrical contacts on the top cap wafer are connected to the top cap electrode. A vent extends from outside of the sensor into the cavity or the capacitance gap. The pressure sensor can include two cavities and two capacitance gaps to form a differential pressure sensor.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 14, 2023
    Assignee: MEI Micro, Inc.
    Inventors: Robert Mark Boysel, Louis Ross
  • Patent number: 11569125
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Patent number: 11557582
    Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Lim Kim, Myung Soo Noh, No Young Chung, Seok Yun Jeong, Young Han Kim