Patents Examined by Paul Rodriguez
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Patent number: 8170844Abstract: A method for estimating a probability of failure of a least-squares ambiguity decorrelation adjustment (LAMBDA) method is provided. The LAMBDA method is used for estimation of double difference carrier phase integer ambiguity. A plurality of condition sets are selected. Each condition set comprises a probability of failure (Pboot-fail) for a boot-strap method of estimation of the double difference carrier phase integer ambiguity, a number of space vehicles (Nsv), and a ratio test tolerance for the LAMBDA method. A plurality of Monte Carlo simulations are run on the plurality of condition sets to obtain a plurality of result sets. Each result set comprises a probability of lambda fail (P?-fail) and a probability of lambda reject (P?-reject) for one condition set of the plurality of condition sets. A lookup table is created with the plurality of result sets. A value of P?-fail for given values of P?-reject, Pboot-fail, and Nsv is estimated through employment of the lookup table.Type: GrantFiled: May 2, 2008Date of Patent: May 1, 2012Assignee: Northrop Grumman Guidance and Electronics Company, Inc.Inventors: Robert J. Buchler, Gang Kevin Liu
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Patent number: 8170859Abstract: Arbitrary, unmodified code and/or software may be executed directly on a host processor operating in a virtualized mode using hardware virtualization support and performance counters. The arbitrary software may be run on the host processor until the host processor exits from the virtualized mode. An end execution time may be calculated in response to the host processor exiting from the virtualized mode. An event may then be handled based on an execution time at which the host processor exited from the virtualized mode and a time at which a scheduled event was to occur.Type: GrantFiled: April 28, 2006Date of Patent: May 1, 2012Assignee: Intel CorporationInventors: Magnus Christensson, Samuel Rydh, Magnus Vesterlund, Johan Rydberg
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Patent number: 8170839Abstract: A tire design method is provided for a tire having a tire tread with a plurality of circumferential ribs separated by circumferential continuous grooves where at least two circumferential ribs are unlocked by at least one circumferential groove. The method may include modeling a lug in each of the at least two circumferential ribs to determine a circumferential shear stiffness and a circumferential shear stiffness per unit length for each rib. The tire design method may further include determining an ideal rib stiffness, an optimal rib stiffness, and a corresponding ideal number of lugs and an optimal number of lugs for each of the at least two circumferential ribs. In one embodiment, the tire design method includes modifying the tire design so the number of lugs in each rib is equal to the optimal number of lugs determined in the tire design method.Type: GrantFiled: April 24, 2009Date of Patent: May 1, 2012Assignee: Bridgestone Americas Tire Operations, LLCInventor: Jon I. Stuckey
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Patent number: 8165864Abstract: Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.Type: GrantFiled: February 8, 2008Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Michael P. Mullen, Marvin J. Rich, James L. Schafer
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Patent number: 8165862Abstract: A method for identifying and evaluating potential computer network configuration problems as related to deployment of one or more computer applications accessed via an associated computer network architecture is described. The method includes emulating the computer network architecture and a capability associated with network interconnections between computer application points of use and associated with the computer network architecture, identifying computer applications hosted at each of the computer systems within the computer architecture, estimating response times for hosted computer applications for a plurality of network architecture interconnection conditions, and determining, based on the response time estimates, at least one network architecture reconfiguration scenario for improving performance of the network architecture with respect to a specific computer application.Type: GrantFiled: February 5, 2008Date of Patent: April 24, 2012Assignee: The Boeing CompanyInventor: Hans Josef Schumacher
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Patent number: 8165866Abstract: An emulation system includes a controller, an emulation calculator, an emulation storage unit, and an interface unit. The emulation calculator includes a device under test (DUT) and emulates the DUT. The emulation storage unit stores emulation data of the DUT emulated by the emulation calculator under the control of the controller. The interface unit distributes and transfers the emulation data to a plurality of computers under the control of the controller.Type: GrantFiled: August 13, 2007Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chi-Ho Cha, Hoon-Sang Jin, Jae-Geun Yun
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Patent number: 8165861Abstract: A simulation method of an electronic circuit or a printed circuit, represented in the form of masks and connections, includes the definition of, on one hand, inputs and outputs of circuit networks, and, on the other, internal components of each network; the formation of a reduced model of each network; and the simulation of the network using this reduced model. In the event of an unsatisfactory simulation result, the modification of one or more networks, the formation of a second reduced model, and the simulation with said new reduced model, are performed. In the event of a satisfactory simulation result, production of the circuit can be undertaken.Type: GrantFiled: November 3, 2006Date of Patent: April 24, 2012Assignee: S.A. EdxactInventor: Stephane Guedon
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Patent number: 8165854Abstract: Methods, systems, and related computer program products for photolithographic process simulation are disclosed. In one preferred embodiment, a resist processing system is simulated according to a Wiener nonlinear model thereof in which a plurality of precomputed optical intensity distributions corresponding to a respective plurality of distinct elevations in an optically exposed resist film are received, each optical intensity distribution is convolved with each of a plurality of predetermined Wiener kernels to generate a plurality of convolution results, and at least two of the convolution results are multiplied to produce at least one cross-product. A weighted summation of the plurality of convolution results and the at least one cross-product is computed using a respective plurality of predetermined Wiener coefficients to generate a Wiener output, and a resist processing system simulation result is generated based at least in part on the Wiener output.Type: GrantFiled: July 8, 2008Date of Patent: April 24, 2012Assignee: Olambda, Inc.Inventor: Haiqing Wei
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Patent number: 8160846Abstract: The method of modeling phase changes due to laser pulse heating utilizes energy equations and a discretizing numerical method to model temperature variation and cavity depth in a substrate material due to laser heating. Both constant and temperature-dependent thermal properties cases are considered.Type: GrantFiled: May 18, 2009Date of Patent: April 17, 2012Assignee: King Fahd University of Petroleum & MineralsInventors: Bekir Sami Yilbas, Saad Bin Mansour
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Patent number: 8160842Abstract: A collection of dwelling unit module designs is created from which multi-family dwelling buildings or the multi-family portion of a mixed-use building may be designed. The module designs each fit onto uniform grid intervals defining a structural support system and fitting a parking layout. A module design may include an individual unit or a stack of units. A graphical user interface to a computer system accommodates defining an outline for the building and filling the outline with dwelling unit modules from the collection. The dwelling unit module designs may be designed and perfected in a manner independent of and in advance of any specific project and project schedule.Type: GrantFiled: May 2, 2008Date of Patent: April 17, 2012Inventor: Arthur A. Klipfel, III
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Patent number: 8160845Abstract: Techniques for emulating operating system jitter on a platform using a given trace are provided. The techniques include calculating a scale factor, wherein the scale factor is equal to a maximum of measured overhead of introducing synthetic jitter on the platform and a resolution of one or more timer calls on the platform, scaling up each of one or more jitter values and each of one or more gaps between each of one or more jitter instances in the trace and an execution period of a benchmark parallel application using the scale factor, introducing synthetic jitter using each of the one or more scaled jitter values and each of the one or more scaled gaps from the trace while running the benchmark parallel application for the scaled execution period to emulate operating system jitter on a platform, and scaling down one or more final time measurements from the benchmark parallel application by the scale factor.Type: GrantFiled: May 30, 2008Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Pradipta De, Ravi Kothari, Vijay Mann
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Patent number: 8160848Abstract: A sample atomic configuration creation part in a control section creates the atomic arrangement data of a sample, and a sample surface height calculation part calculates a sample surface height for every mesh. A probe profile creation part creates the atomic arrangement data of a probe, and a probe surface height calculation part calculates the height of the probe surface for every mesh. A probe scanning part supplies the coordinate of a scanning start position in the scanning range to a collision height specification part. The collision height specification part calculates the distance between the sample surface and the probe in each mesh. Calculation of this distance is repeated for all meshes of the probe at the coordinate of this measuring position.Type: GrantFiled: March 29, 2007Date of Patent: April 17, 2012Assignees: Mizuho Information & Research Institute, Inc., Waseda UniversityInventors: Naoki Watanabe, Masaru Tsukada, Katsunori Tagami
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Patent number: 8160858Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method performs circuit pruning for each of distinct vectors. The circuit pruning includes identifying an active circuit for each vector. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.Type: GrantFiled: December 16, 2010Date of Patent: April 17, 2012Assignee: Cadence Design Systems, Inc.Inventors: Ken Tseng, Kevin Chou
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Patent number: 8160861Abstract: The system comprises a component model for modelling aspects of the hardware component, and feature extraction logic for extending the component model to cause the component model, when executing, to output one or more features identifying execution behavior of the component model. A statistical model is then arranged to receive the one or more features output by the component model, and to generate the output dependent on one or more features. The component model may not explicitly model features that can be used to effectively predict values of the observable property, features that a statistical model depends on may still be captured in the underlying logic and implementation of the component model. By extracting features identifying execution behavior of the component model, this can provide a suitable input to the statistical model.Type: GrantFiled: January 14, 2008Date of Patent: April 17, 2012Assignee: ARM LimitedInventors: Simon Andrew Ford, Paul Halliday Peeling
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Patent number: 8155938Abstract: The invention provides methods for enhancing circuit reliability under statistical process variation. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may induce a not-so-rare system failure. To combat this, the invention discloses the method called “Statistical Blockade,” a Monte Carlo-type technique that allows the efficient filtering—blocking—of unwanted samples insufficiently rare in the tail distributions of interest, with speedups of 10-100×. Additionally, the core Statistical Blockade technique is further extended in a “recursive” or “bootstrap” formulation to create even greater efficiencies under a much wider variety of circuit performance metrics, in particular two-sided metrics such a Data Retention Voltage (DRV) which prior Monte Carlo techniques could not handle.Type: GrantFiled: March 28, 2008Date of Patent: April 10, 2012Assignee: Carnegie Mellon UniversityInventors: Amith Singhee, Rob Rutenbar
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Patent number: 8155942Abstract: The disclosed methods, systems, and software are described for optimizing well placement in a reservoir field. A geological model of a reservoir field, a grid defining a plurality of cells, one or more wells to be located within the plurality of cells, and an objective function are all provided. The geological model is associated with the grid defining the plurality of cells. The locations of the wells are represented by continuous well location variables associated with a continuous spatial domain. A gradient of the objective function is calculated responsive to the continuous well location variables. The locations of the wells are then adjusted responsive to the calculated gradient of the objective function. Iterative calculation of the gradient and adjustment of the wells continue until the well locations are optimized. A visual representation of the reservoir field can be generated based on the optimized well placements.Type: GrantFiled: February 19, 2009Date of Patent: April 10, 2012Assignee: Chevron U.S.A. Inc.Inventors: Pallav Sarma, Wen Hsiung Chen
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Patent number: 8155928Abstract: A scheduling system and a CAD system are used to prepare a construction plan in plant construction simulation. A construction work managed by the scheduling system and a plant part used in the construction work and managed by the CAD system, are managed in association with each other. When the plant part is broken down into a plurality of lower plant parts constituting the plant part, as a plurality of lower construction works of the construction work, the processing for associating the lower plant parts with the lower construction works is performed. Data for mutually associating the construction works and the plant parts based on the processing is generated. The generated data is used to mutually link the scheduling system and the CAD system, and a situation in which appropriate parts are installed as progress of the construction work, is displayed.Type: GrantFiled: January 15, 2009Date of Patent: April 10, 2012Assignee: Hitachi-GE Nuclear Energy, Ltd.Inventors: Hisanori Nonaka, Kenji Araki, Norito Watanabe, Yoshibumi Fukuda, Toshiyuki Miyake, Masatoshi Takada, Hisako Okada
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Patent number: 8150665Abstract: A method and product for modeling and managing requirements in a complex integrated system, which comprises creating a set of requirements which can be implemented within all the components of the complex integrated system. Each requirement may be characterized as a point on the circumference of a circle, the characterization being an assignment of a requirement type. This type determines which circle the point will be located on, assigning a unique immutable numerical value to each requirement that determines in which order the point is placed on the previously determined circle. A location is also determined for each requirement. The location may determine the position of the requirement in relation to other requirements on the circumference of one of the set of circles. Sectors are also formed within the set of circles, as a function of a set of architectural principles and interfaces are identified between points, represented as chords.Type: GrantFiled: March 5, 2009Date of Patent: April 3, 2012Assignee: International Business Machines CorporationInventors: Chandrajit Choudhury, Kumar Mani, Purushothaman Kunnath Narayanan, Senthil Kumar Thiagarajan
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Patent number: 8150664Abstract: The present invention relates generally to a software architecture for simulation of physical entities. The invention provides an object-oriented container based framework architecture for simulator software implementations, methods, and objects in a time domain on a distributed computer network. The invention further provides an interface system and a plug-in definition which allows compartmentalization of participants in the container and easy extensibility of the system.Type: GrantFiled: February 20, 2009Date of Patent: April 3, 2012Assignee: Zedasoft, Inc.Inventors: Robert Allen Hatcherson, Richard Keith Holt, Stephen Edward Tarter, Jeremiah Jay Johnson, Frederick Bryan Fleury, George William Estep, II
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Patent number: 8145458Abstract: An automated approach is provided for evaluating stress upon analog components embedded in a digital electronic circuit design. The approach includes establishing a computer readable circuit definition of the digital electronic circuit design. The circuit definition is then partitioned into a plurality of circuit portions, which are re-defined to form a plurality of analog topologies. The analog topologies are adapted for automatic analog simulation one independent of the other, with all digital components substituted by at least one subcircuit including instantiation of a corresponding input output (IO) buffer model. Automatic analog simulation is carried out upon the analog topologies to generate simulated results data, which are automatically postprocessed to generate worst-case stress measurement data for one or more critical components identified in the analog topologies.Type: GrantFiled: April 19, 2007Date of Patent: March 27, 2012Assignee: Cadence Design Systems, Inc.Inventors: Taranjit Singh Kukal, Sankaran Dharmarajan