Abstract: A line structure for fan-out circuit having a dense-line area and a fan-out area is provided. The line structure includes a plurality of dense lines arranged in the dense-line area parallel to a first direction, a plurality of pads disposed in the fan-out area, and a plurality of connecting lines arranged in the fan-out area parallel to a second direction. The connecting lines respectively connect one of the dense lines with one of the pads, wherein at least one of the connecting lines is a wavy line.

Abstract: Photonic devices monolithically integrated with CMOS are disclosed, including sub-100 nm CMOS, with active layers comprising acceleration regions, light emission and absorption layers, and optional energy filtering regions. Light emission or absorption is controlled by an applied voltage to deposited films on a pre-defined CMOS active area of a substrate, such as bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, Thin-Film GOI.

Abstract: Methods are disclosed herein for forming conductive patterns having small pitches. An exemplary method includes forming a metal line in a first dielectric layer. The metal line has a first dimension along a first direction and a second dimension along a second direction that is different than the first direction. The method includes forming a patterned mask layer having an opening that exposes a portion of the metal line along an entirety of the second dimension and etching the portion of the metal line exposed by the opening of the patterned mask layer until reaching the first dielectric layer. The metal line is thus separated into a first metal feature and a second metal feature. After removing the patterned mask layer, a barrier layer is deposited over exposed surfaces of the first metal feature and the second metal feature and a second dielectric layer is deposited over the barrier layer.

Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.

Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.

Abstract: Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.

Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene

Abstract: A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.

Abstract: A semiconductor device includes a semiconductor element, a base body, a conductive adhesive member, and a sealing member. The semiconductor element includes a substrate, a semiconductor element structure provided on the substrate, and p-electrode and n-electrode provided on the semiconductor element structure. The semiconductor element is disposed on the base body. The conductive adhesive member electrically connects the p-electrode and the n-electrode to the base body. The sealing member is provided to cover the semiconductor element on an upper surface of the base body. The conductive adhesive member contains particles selected from a group of (i) surface-treated particles having a particle diameter of 1 nm or more and 100 ?m or less and (ii) particles that coexist with a dispersing agent.

Abstract: Processes for automatic registration between a solid circuit die and electrically conductive interconnects, and articles or devices made by the same are provided. The solid circuit die is disposed on a substrate with contact pads aligned with channels on the substrate. Electrically conductive traces are formed by flowing a conductive liquid in the channels toward the contact pads to obtain the automatic registration.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: A display device including: a substrate including a display area, a peripheral area, and a pad area; a first main voltage line in the peripheral area, and a first connector extending from the first main voltage line to the pad area; and a second main voltage line in the peripheral area, and a second connector extending from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a first and second layer overlapping each other with a first insulating layer therebetween, the first insulating layer is in the display area and the peripheral area, the peripheral area includes an open area exposing the first and second connector and surrounding the display area, and the first insulating layer includes slits between the first and second connector and extending from an end of the first insulating layer toward the display area.

Abstract: A light emitting device includes one or more light emitting elements, a light transmissive member, and a light reflective member. The one or more light emitting elements each includes an upper surface. The light transmissive member has an upper surface and a lower surface. The light reflective member covers surfaces of the light transmissive member and lateral surfaces of the one or more light emitting elements so as to expose the upper surface of the light transmissive member. The upper surface area of the light transmissive member is smaller than a sum of the upper surface areas of the one or more light emitting elements, and the lower surface area of the light transmissive member is larger than a sum of the upper surface areas of the one or more light emitting elements.

Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Abstract: A lighting device is provided. The lighting device may include an organic light emitting diode arranged on one surface of a first substrate, the organic light emitting diode including a first electrode, an organic light emitting layer and a second electrode, and the first electrode is made of a transparent conductive material having a resistance value of 2,800-5,500? in each pixel, and has light scattering particles dispersed therein. Thus, even when a resistor of the organic light emitting layer is removed from a pixel due to a contact between the first electrode and the second electrode, it is possible to prevent an over current from being applied to the corresponding pixel through a resistor of the first electrode.

Abstract: A micro-transfer printable electronic component includes one or more electronic components, such as integrated circuits or LEDs. Each electronic component has device electrical contacts for providing electrical power to the electronic component and a post side. A plurality of electrical conductors includes at least one electrical conductor electrically connected to each of the device electrical contacts. One or more electrically conductive connection posts protrude beyond the post side. Each connection post is electrically connected to at least one of the electrical conductors. Additional connection posts can form electrical jumpers that electrically connect electrical conductors on a destination substrate to which the printable electronic component is micro-transfer printed. The printable electronic component can be a full-color pixel in a display.

Abstract: Some embodiments include a magnetic tunnel junction device having a first magnetic electrode, a second magnetic electrode, and a tunnel insulator material between the first and second magnetic electrodes. A tungsten-containing material is directly against one of the magnetic electrodes. In some embodiments the tungsten-containing material may be in a first crystalline lattice arrangement, and the directly adjacent magnetic electrode may be in a second crystalline lattice arrangement different from said first crystalline lattice arrangement. In some embodiments the tungsten-containing material, the first magnetic electrode, the tunnel insulator material and the second magnetic electrode all comprise a common crystalline lattice arrangement.

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

Abstract: A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a dielectric layer at a same level as the dummy gate stack, removing the dummy gate stack to form an opening in the dielectric layer, filling a metal layer extending into the opening, and etching back the metal layer, with remaining portions of the metal layer having edges lower than a top surface of the dielectric layer. The opening is filled with a conductive material, and the conductive material is over the metal layer. The metal layer and the conductive material in combination form a replacement gate. A source region and a drain region are formed on opposite sides of the replacement gate.