Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

Abstract: An atomic orbital based memory storage is provided that includes a plurality of surface atoms forming dangling bonds (DBs) and a subset of the plurality of surface atoms passivated with spatial control to form covalent bonds with hydrogen, deuterium, or a combination thereof. The atomic orbital based data storage that can be rewritten and corrected as needed. The resulting data storage is also archival and capable of high data densities than any known storage as the data is retained in a binary storage or a given orbital being passivated or a dangling bond (DB). A method of forming and reading the atomic orbital data storage is also provided. The method including selectively removing covalent bonds to form dangling bonds (DBs) extending from a surface atom by hydrogen lithography and imaging the covalent bonds spatially to read the atomic orbital data storage.

Abstract: A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, a signal is generated to adjust the first digitally-controlled pump voltage level to a second digitally-controlled pump voltage level.

Abstract: A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching devices coupled between the first and second data lines and first and second input terminals of the sense amplifier, third and fourth switching devices coupled between the first and second data lined and first and second nodes, fifth and sixth switching devices coupled between the first and second nodes and the reference voltage node, and first and second capacitive devices coupled between the first and second nodes and second and first input terminals. Each of the first through fourth switching devices is switched on and each of the fifth and sixth switching devices is switched off in a first operational mode, and each of the first through fourth switching devices is switched off and each of the fifth and sixth switching devices is switched on in a second operational mode.

Abstract: A magnetic memory device includes a spin orbit torque (SOT) generator configured to generate a SOT, and a vertical magnetic recording layer connected to a main surface of the SOT generator at one end thereof, and is configured to record information using a SOT generated by the SOT generator and a current flowing in the vertical magnetic recording layer in combination. The magnetic memory device includes an insulating layer on one end of the vertical magnetic recording layer in an extension direction of the vertical magnetic recording layer, and a fixed layer on the insulating layer in the extension direction of the vertical magnetic recording layer.

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.

Abstract: An example of an apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

Abstract: Apparatuses and methods related to an artificial intelligence accelerator in memory are disclosed. An apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

Abstract: This spin-orbit torque type magnetization rotational element (10) is provided with: a spin-orbit torque wiring (2); a first ferromagnetic layer (1) that is laminated on the spin-orbit torque wiring; a first nonmagnetic metal layer (3) and a second nonmagnetic metal layer (4) that are connected to the spin-orbit torque wiring at positions flanking the first ferromagnetic layer in a plan view from the second direction, and a first insulating layer (31) surrounding the spin-orbit torque wiring, wherein the gravity center (G) of the first ferromagnetic layer is positioned on a side closer to the first nonmagnetic metal layer or the second nonmagnetic metal layer than is a reference point (S) located at the center between the first and second nonmagnetic metal layers in the first direction, and the first insulating layer is any one selected from the group consisting of silicon nitride, aluminum nitride, aluminum oxide, and magnesium oxide.

Abstract: Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information as part of operating the memory system and a pin of a second type. The apparatus may also include a circuit coupled with the memory system, the circuit including a resistor that is coupled with the pin of the second type. The memory system may include a controller that selects a value for the resistor and generates a code as part of a memory management operation to determine one or more operating conditions of the memory system based on selecting the value. The memory system controller may also determine an error associated with the code based on generating the code and the selected value of the resistor.

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, and a reference layer, forming a cylindrical diode structure above and in electrical contact with the SOT-MRAM cell stack, forming a write line disposed in electrical contact with the SHE rail, and forming a read line disposed above and adjacent to an outer cylindrical electrode of the diode structure.

Abstract: A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer.

Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Abstract: Methods, apparatus, systems and articles of manufacture to establish a data pipeline between cloud computing platforms. An apparatus includes at least one memory, machine readable instructions in the apparatus, and processor circuitry to execute the machine readable instructions to at least extract a data producer name from data, the data to be provided from a data producer to a data consumer, identify a buffer identifier based on a mapping of the data producer name to the buffer identifier, cause transmission of the data to a buffer associated with the buffer identifier, and cause transmission of the data from the buffer to the data consumer based on an association between the buffer identifier and a data consumer name, the data consumer name corresponding to the data consumer.