Patents Examined by Pho M. Luu
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Patent number: 11723296Abstract: A system and method for storing information in a quantum computer using a quantum storage ring. The method comprises cooling ions in the quantum storage ring to a low temperature; and binding the ions into a lattice structure, forming an ion Coulomb crystal.Type: GrantFiled: May 1, 2020Date of Patent: August 8, 2023Assignee: U.S. Department of EnergyInventors: Kevin Brown, Thomas Roser
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Patent number: 11723208Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other inType: GrantFiled: March 15, 2022Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Dongku Kang
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Patent number: 11723214Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.Type: GrantFiled: April 26, 2022Date of Patent: August 8, 2023Assignee: SK hynix Inc.Inventor: Hwang Yeon Kim
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Patent number: 11715529Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: March 8, 2022Date of Patent: August 1, 2023Assignee: KIOXIA CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
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Patent number: 11705202Abstract: A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.Type: GrantFiled: October 12, 2021Date of Patent: July 18, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zhipeng Dong, Venkatagirish Nagavarapu, Haibo Li
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Patent number: 11694748Abstract: A method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.Type: GrantFiled: April 8, 2022Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
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Patent number: 11694743Abstract: A chip system includes a first chip, a first DRAM, a second chip and a second DRAM. The first chip includes a first DRAM controller and a first serial transmission interface. The first DRAM is coupled to the first DRAM controller. The second chip includes a second DTAM controller and a second serial transmission interface. The second serial transmission interface is coupled to the first serial transmission interface. The second DRAM is coupled to the second DRAM controller. When the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface; and the second chip stores the second data into the second DRAM via the second DRAM controller.Type: GrantFiled: June 6, 2021Date of Patent: July 4, 2023Assignee: Realtek Semiconductor Corp.Inventor: Ching-Sheng Cheng
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Patent number: 11696450Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.Type: GrantFiled: November 1, 2021Date of Patent: July 4, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11696451Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.Type: GrantFiled: November 1, 2021Date of Patent: July 4, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11688471Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.Type: GrantFiled: March 8, 2022Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Hong-Yan Chen, Yingda Dong
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Patent number: 11688477Abstract: Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.Type: GrantFiled: October 15, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11675500Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.Type: GrantFiled: February 5, 2021Date of Patent: June 13, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Youn Cheul Kim, Richard S. Chernicoff, Khandker Nazrul Quader, Robert D. Norman, Tianhong Yan, Sayeef Salahuddin, Eli Harari
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Patent number: 11670372Abstract: Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.Type: GrantFiled: October 27, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Hong-Yan Chen, Yingda Dong
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Patent number: 11670368Abstract: A method for reading memory cells is described. The method may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.Type: GrantFiled: October 27, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
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Patent number: 11670371Abstract: The semiconductor memory device includes a memory block including a plurality of memory strings, a pass circuit connected between local word lines of the memory block and global word lines and configured to connect the local word lines to the global word lines in response to a block selection signal, and a voltage providing circuit configured to generate an operation voltage during a program or read operation, apply the operation voltage to the global word lines, and discharge the global word lines when the program operation or the read operation is completed, and the pass circuit is configured to control the local word lines to be in a floating state after the program operation or the read operation is completed and before discharging the global word lines.Type: GrantFiled: June 24, 2021Date of Patent: June 6, 2023Assignee: SK hynix Inc.Inventor: Jin Su Park
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Patent number: 11664059Abstract: A memory system may include a magnetic tunnel junction stack, a first high resistance tunnel barrier, and a first voltage controlled magnetic anisotropy write layer. The first voltage controlled magnetic anisotropy write layer may be adjacent the high resistance tunnel barrier, and the voltage controlled magnetic anisotropy write line may include a magnetic material in direct contact with a high resistance tunnel barrier.Type: GrantFiled: June 2, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Dimitri Houssameddine, Saba Zare, Heng Wu, Karthik Yogendra
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Patent number: 11664074Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.Type: GrantFiled: June 2, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Nevil N. Gajera, Lingming Yang, Yen Chun Lee, Jessica Chen, Francesco Douglas Verna-Ketel
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Patent number: 11657870Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.Type: GrantFiled: July 21, 2021Date of Patent: May 23, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
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Patent number: 11658159Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.Type: GrantFiled: September 24, 2021Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Saravanan Sethuraman, Tonia Morris, Siaw Kang Lai, Yee Choong Lim, Yu Ying Ong
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Patent number: 11651822Abstract: In a method of operating a nonvolatile memory device, the nonvolatile memory device includes a memory block that includes a plurality of memory cells and is connected to a plurality of wordlines. A data write command is received. Based on the data write command, a first program operation is performed on some wordlines among the plurality of wordlines connected to the memory block. At least one of the some wordlines on which the first program operation is performed is detected as a no-coupled wordline. Without the data write command, a second program operation is performed on an open wordline on which the first program operation is not performed and adjacent to the no-coupled wordline.Type: GrantFiled: January 18, 2022Date of Patent: May 16, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Seongho Ahn