Abstract: A memory system including a memory device suitable for performing, in stages, a program loop including a program operation and a program verification operation on each page within a memory block selected among a plurality of memory blocks, updating a maximum number of program loops for the selected memory block by comparing a number of program loops on each page, which are performed until the program verification operation is processed as a pass on the page, with a current maximum number of program loops for the selected memory block, and storing the updated maximum number of program loops for the selected memory block as program pass information of the selected memory block; and a controller suitable for managing the selected memory block as a bad block based on the program pass information of the selected memory block.

Abstract: A flexible tactile actuator includes a tactile transmitter configured to be flexible and including magnetic particles capable of being polarized in response to an external magnetic field and a matrix layer including the magnetic particles, a magnetic field generator disposed below the tactile transmitter and configured to generate a magnetic field in the tactile transmitter, and an elastic member provided in a shape of a film, having at least a portion in surface contact with the magnetic field generator, and attached to be in surface contact with one of a top surface and a bottom surface of the tactile transmitter.

Abstract: A magnetoresistive device includes a spin-orbit-torque (SOT) electrode layer, and a first magnetic layer, a first non-magnetic layer, and a second magnetic layer sequentially stacked over the SOT electrode layer. An interface layer is located between the SOT electrode layer and the first magnetic layer, and an etch stop layer covers a surface portion of the SOT electrode layer and is located adjacent the interface layer. The interface layer includes a metal having a spin diffusion length that is greater than a thickness of the interface layer, and the etch stop layer includes an oxide or nitride material of the metal.

Abstract: A reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation and a read operation on the memory cell array. The control logic is configured to control an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform an SLC program operation on memory cells included in a selected page among the plurality of memory cells, compares the number of first fail bits counted by performing a normal sensing operation on the selected page and the number of second fail bits counted by performing a multi-sensing operation on the selected page, and corrects at least one evaluation time to be used for a read operation based on a result of the comparison.

Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node, and a single selection transistor coupled between the common node and a single bit line. A first output of the volatile memory cell is coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, is not connected to any node outside the volatile memory cell.

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.

Abstract: A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii.

Abstract: There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.

Abstract: The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.

Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

Abstract: A substrate treating apparatus and a substrate transporting method. A platform is placed on a first ID block, and a platform is placed on a second ID block. A currently-used carrier platform is provided only on the first ID block. A substrate is transported in both a forward path and a return path between the first ID block and an IF block. The substrate is sent in the return path from the IF block to the second ID block disposed between a coating block and a developing block without being transported from the IF block to the first ID block. Consequently, transportation process in the return path by the coating block disposed between the first ID block and the second ID block is reduced. As a result, an entire throughput of a substrate treating apparatus can be enhanced.

Abstract: A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, the first digitally-controlled pump voltage level applied to the charge pump is caused to change to a second digitally-controlled pump voltage level.

Abstract: A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil.

Abstract: In a technique for inducing local electric field controlled magnetization, despite the absence of magnetic components, there is provided a novel heterostructure, a semiconductor device thereof, or an array of semiconductor devices. The heterostructure includes a semiconductor substrate carrying a plurality of layers forming at least one heterojunction and hosting a two-dimensional electron gas layer when one of the layer of the plurality of layers is bounded to an interacting layer being a chiral or a biological macromolecule assembly.

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

Abstract: An electronic device includes a memory device and a timing controller configured to output control signals, which are generated using a first clock signal, to the memory device, generate first captured data by capturing data, which is output from the memory device, using the first clock signal in response to the control signals, and generate control signals using a second clock signal and output the control signals to the memory device when the first captured data is not valid data.

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

Abstract: A memory system includes: a nonvolatile memory and a memory controller. The nonvolatile memory includes: a first memory cell and a second memory cell each configured to store data and coupled in parallel to a bit line, a first word line coupled to the first memory cell, and a second word line coupled to the second memory cell and differing from the first word line. The first and second memory cell face each other between the first word line and the second word line. The memory controller is configured to read first data from the first memory cell, read second data from the second memory cell, and decode data stored in the first memory cell based on the first data and the second data.