Patents Examined by Phuc Dang
  • Patent number: 10204982
    Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Qing Liu, Nicolas Loubet
  • Patent number: 10205055
    Abstract: The invention discloses a light engine array having at least an anode and a cathode comprising: a first type semiconductor layer; an active layer; and a second type semiconductor layer; a cathode electrode has a conductive metal layer in electrical contact with a portion of the first type semiconductor layer, and the second type semiconductor layer to form a short circuit structure in a common cathode region; and an anode electrode has the conductive metal layer and coupled to a portion of the first type semiconductor layer; wherein, the anode electrode is electrically isolated with the active layer and the second type semiconductor layer in a sub-pixel region.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: February 12, 2019
    Assignee: HIPHOTON CO., LTD.
    Inventors: Chen-Fu Chu, Chen-Hsien Chu
  • Patent number: 10203526
    Abstract: A semiconductor junction may include a first layer and a second layer. The first layer may include a first semiconductor material and the second layer may be deposited on the first layer and may include a second material. The valence band maximum of the second material is higher than a conduction band minimum of the first semiconductor material, thereby allowing a flow of a majority of free carriers across the semiconductor junction between the first and second layers to be diffusive.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: February 12, 2019
    Assignee: THE UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE
    Inventors: Raphael Tsu, Michael Fiddy, Tsinghua Her
  • Patent number: 10199449
    Abstract: A display device includes: a substrate; pixels, the pixels each including at least one transistor and a light emitting device connected to the transistor; data lines and scan lines connected to the pixels; and a power line supplying power to the light emitting device. The transistor includes an active pattern on the substrate, source and drain electrodes each connected to the active pattern, a gate electrode on the active pattern, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer, which are sequentially stacked, and a protective layer provided on the interlayer insulating layer. The third interlayer insulating layer includes a concave part in a region in which the light emitting device and the second conductive layer overlap with each other, and the second conductive layer is in the concave part.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yang Wan Kim, Hyung Jun Park, Jae Yong Lee, Byung Sun Kim, Su Jin Lee
  • Patent number: 10199599
    Abstract: An organic light emitting diode device can have an enhanced thin film encapsulation layer for preventing moisture from permeating from the outside. The thin film encapsulation layer can have a multilayered structure in which one or more inorganic layers and one or more organic layers are alternately laminated. A barrier can be formed outside of a portion of the substrate on which the organic light emitting diode is formed. The organic layers of the thin film encapsulation layer can be formed inside an area defined by the barrier.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Nam-Jin Kim, Chul-Hwan Park
  • Patent number: 10199507
    Abstract: A thin film transistor and a method of manufacturing the same, and a display device and a method of manufacturing the same are disclosed, in which the thin film transistor substrate comprises an active layer formed on a substrate; a gate electrode controlling electron transfer within the active layer; a source electrode connected with one end area of the active layer; a drain electrode connected with the other end area of the active layer; and a light-shielding layer formed under the active layer to shield light from entering the active layer.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: February 5, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Seung Joon Jeon, Ki Sul Cho, Seong Moh Seo
  • Patent number: 10192933
    Abstract: The present disclosure discloses a manufacturing method of organic light emitting device, and the steps of the manufacturing method comprises: manufacturing a bottom electrode on a base substrate; manufacturing an organic electro-emitting assembly on the bottom electrode by evaporation techniques and lithography techniques; and manufacturing a top electrode on the organic electro-emitting assembly. An organic light emitting device manufactured by the aforementioned method is further disclosed in the present invention. Hole transport layers corresponded to every emitting layers is manufactured by lithography technologies in the present disclosure; therefore, no fine metal mask is needed in use to reduce production cost and time; furthermore, properties of the organic light emitting device is increased simultaneously.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: January 29, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Hsiang Lun Hsu, Meng Zhao
  • Patent number: 10192902
    Abstract: A method for manufacturing a LTPS array substrate includes: forming a source electrode and a drain electrode on a substrate, forming a poly-silicon layer in a first region and a second region of the substrate including the source electrode and the drain electrode, such that the poly-silicon layer of the first region has a thickness greater than that of the second region and the poly-silicon layer of the first region partially covers the source electrode and the drain electrode; passivating a surface of the poly-silicon layer in order to turn a part of the poly-silicon layer of the second region and the first region that is adjacent to the surface into an insulating layer; and forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The LTPS technical process is simple and can reduce the producing costs.
    Type: Grant
    Filed: December 24, 2017
    Date of Patent: January 29, 2019
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd, Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Cong Wang, Peng Du, Xiaoxiao Wang
  • Patent number: 10193068
    Abstract: Provided is a method of manufacturing a thin film transistor satisfying the relation of L<5 ?m. The method includes a process of forming a streak portion by performing transfer printing on a support using a release member which is provided with an ink streak portion for forming source and drain electrodes and has mold releasability, and baking the streak portion to thereby form the source electrode constituted by a conductor and the drain electrode constituted by a conductor. In the method manufacturing a thin film transistor in which the source and drain electrodes obtained above, a semiconductor layer, an insulator layer, and a gate electrode constituted by a conductor are laminated, after the baking, in a laminated cross section of the thin film transistor to be manufactured is set to A and a channel length thereof is set to L, the ink streak portion is provided so as to satisfy the condition of L/A?0.05.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: January 29, 2019
    Assignees: DIS Corporation, National University Corporation Yamagata University
    Inventors: Tomoko Okamoto, Kenichi Yatsugi, Yoshinori Katayama, Kenjiro Fukuda, Daisuke Kumaki, Shizuo Tokito
  • Patent number: 10186567
    Abstract: A display apparatus has pixel area to emit light, a transmission area to transmit external light, and wirings including scan wiring, data wiring, and power wiring. The data and power wiring are adjacent to the pixel area and transmission area. An organic light-emitting device is in the pixel area. At least one of the data wiring or the power wiring includes first wiring and second wiring. The first wiring is adjacent to the pixel area and including a mother wiring having a first width. The second wiring includes a plurality of branched wirings that branch from the mother wiring. The branched wirings are adjacent to the transmission area, and a width of each of the branched wirings is less than the first width.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Cheolyun Jeong, Sunghoon Kim
  • Patent number: 10181566
    Abstract: An electrically conductive OLED carrier includes in this order a glazing substrate; an electrode arranged in a metal grid made up of strands; an electrically insulating light extraction layer under the metal grid; and a layer partially structured in its thickness. The layer of refractive is of index n3 of 1.7 to 2.3, and is located on the light extraction layer. The partially structured layer is formed from a region structured with cavities at least partially containing the metal grid; and from another region, called the low region, located on the light extraction layer. The separation H between the surface of the structured region called the high surface, and therefore that furthest from the substrate, and the surface of the metal grid called the upper surface, and therefore that furthest from the substrate is, in absolute value, smaller than or equal to 100 nm.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 15, 2019
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventors: Denis Guimard, Georges Zagdoun
  • Patent number: 10177074
    Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: January 8, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Soon Wei Wang, Hoe Kit Liew How Kat Ley
  • Patent number: 10177212
    Abstract: Disclosed herein is an electroluminescent display device capable of improving reliability of a contact portion between low-potential supply line and a cathode electrode of an organic light emitting diode. The electroluminescent display device includes a low potential voltage supply line disposed on a display panel to supply a low potential voltage to the display panel; a cathode electrode overlapped with the low potential voltage supply line and having at least one contact portion; and an auxiliary cathode electrode overlapped with the low potential voltage supply line and the cathode electrode to connect the low potential voltage supply line to the cathode electrode, wherein a bank layer is disposed between the cathode electrode and the auxiliary cathode electrode to cover a rim of the auxiliary cathode electrode, or the cathode electrode covers a rim of the auxiliary cathode electrode and an inorganic insulation layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 8, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Heedong Choi
  • Patent number: 10170723
    Abstract: An organic light emitting element according to an exemplary embodiment of the present disclosure includes a first electrode, a second electrode, an emission layer between the first electrode and the second electrode, an electron injection layer between the second electrode and the emission layer, and a barrier layer between the electron injection layer and the second electrode, wherein a work function of the barrier layer is larger than a work function of the second electrode.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: January 1, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Kyu Seo, Dong Chan Kim, Won Jong Kim, Eung Do Kim, Jong Hyuk Lee, Da Hea Im, Sang Hoon Yim, Yoon Hyeung Cho, Chang Woong Chu, Won Suk Han
  • Patent number: 10164107
    Abstract: In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Yung Jung Chang
  • Patent number: 10157822
    Abstract: Electrical interconnects having a non-linear conductive pathway, and related apparatuses and methods, are disclosed herein. In some embodiments, an electrical interconnect may include a non-linear conductive pathway electrically coupling top and bottom conductive portions. In some embodiments, an electrical interconnect may include a non-linear conductive pathway that propagates an electrical signal generating electromagnetic fields with an electrical field orthogonal to the direction of electromagnetic-wave propagation. In some embodiments, an electrical interconnect may include a non-linear conductive pathway portion and a linear conductive pathway portion. Also disclosed are connectors including an electrical interconnect having a non-linear conductive pathway.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Tae Young Yang, Guosong Lin, Ling Zheng, Daqiao Du
  • Patent number: 10151942
    Abstract: In a display device using a substrate having flexibility, a drop in reliability due to defects such as cracks in the case where a substrate is made to curve is controlled. A display device is provided including a first substrate having flexibility, the first substrate including a curved part, an organic film covering a first surface of the first substrate and a second surface opposing the first surface in the curved part; and a pixel part and a drive circuit part arranged on the first surface.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: December 11, 2018
    Assignee: Japan Display Inc.
    Inventor: Hsiang Yuan Cheng
  • Patent number: 10141380
    Abstract: Discussed is an organic light emitting display device including a plurality of pixels, where red sub pixels and blue sub pixels of adjacent pixels are aligned in a first direction and are also aligned in a second direction, the second direction being a direction that intersects the first direction. Also, the green pixels of adjacent pixels are aligned in the first direction and are also aligned in the second direction. And the at least one green sub pixel of each pixel is disposed between the at least one red sub pixel and the at least one blue sub pixel of the each pixel, and the at least one green sub pixel is offset from the at least one red sub pixel and the at least one blue sub pixel in the first direction and the second direction in the each pixel.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 27, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: EuiHyun Chung, Yongmin Jeong
  • Patent number: 10141541
    Abstract: The present invention provides a package component of an Organic Light Emitting Diode (OLED) device and a package method thereof, and a display device. A first blocking layer covers the OLED device. A side of the first blocking layer far away from the OLED device includes a first pattern region and a second pattern region alternately set along a predetermined direction, and thickness of the first blocking layer at the first pattern region is smaller than that at the second pattern region.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 27, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Wenjie Li, Ting Shi
  • Patent number: 10140395
    Abstract: It is provided a computer-implemented method for simulating the machining of a workpiece with a cutting tool having at least one cutting part and at least one non-cutting part. The method comprises providing a set of dexels that represents the workpiece, a trajectory of the cutting tool, and a set of meshes each representing a respective cutting part or non-cutting part of the cutting tool. And then the method comprises for each dexel computing, for each mesh, the extremity points of all polylines that describe a time diagram, and testing a collision of the cutting tool with the workpiece along the dexel based on the lower envelope of the set of all polylines. Such a method improves the simulating of the machining of a workpiece.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 27, 2018
    Assignee: Dassault Systemes
    Inventors: Nicolas Montana, Romain Nosenzo