Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Abstract: One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence.

Abstract: A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.

Abstract: A method for multi-dimensional decoding, the method may include receiving a multi-dimensional encoded codeword that comprises a payload and a redundancy section; wherein the payload comprises data and an error detection process signature; evaluating, during a multi-dimensional decoding process of the multi-dimensional encoded codeword, an hypothesis regarding a content of the payload; applying on the hypotheses an error detection process to provide an indication about a validity of the hypotheses; and proceeding with the multi-dimensional decoding process and finding a next hypothesis to be error detection process validated when the hypothesis is invalid.

Abstract: A method for determining two bits errors in transmission of 128 bits and the device for realization of this method is provided. By the method and device, the two error bits transferred bits can be determined and corrected by using least bits in operation. Therefore, the amount of data in transmission is increased with a least quantity and thus the transmission quality is not affected.

Abstract: Failed transport blocks can be retransmitted when the number of layers is different compared to the number of layers for re-transmission. Mapping tables can be used for retransmitting the failed packets when a user equipment reported rank is different from the transmitted rank. In addition, an indication can be sent to the user equipment to indicate the failed transport blocks when the network decides to use a different codeword for transmitting a failed packet.

Abstract: A memory test system may include: a data storage device including a nonvolatile memory device, and a controller configured to control an operation of the nonvolatile memory device; and a test device configured to: request a test to the data storage device; request, to the data storage device, an output of a variable to be generated through driving of a firmware for performing the test, while the test is performed in the data storage device; and determine whether the firmware is normally driven based on the variable outputted from the data storage device.

Abstract: A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.

Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

Abstract: A method of operation of a decoder includes receiving first data at the decoder. The method further includes generating second data at the decoder based on the first data. The second data is generated by adjusting an error locator polynomial based on an error parity of the first data.

Abstract: A coded signal is received via a physical channel. The coded signal is encoded by a parity check matrix. In some examples, the coded signal is low density parity check-encoded. The coded signal is decoded to determine a result signal. Said decoding alternatingly updates, for each one of a number of iterations, bit node values representing bits of the result signal and check node values representing constrains of the parity check matrix. In some examples, the decoding determines the result signal at a first precision and updates at least partly at a second precision which is lower than the first precision. In further examples, the number of iterations is dynamically adjusted.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Method and apparatus for interleaving is provided.

Abstract: A method is described. The method includes fragmenting data of an object for storage into an object storage system into multiple data fragments and performing a first error correction encoding process on the data to generate one or more parity fragments for the object. The method also includes sending the multiple data fragments and the one or more parity fragments over a network to different storage servers of the object storage system. The method also includes performing the following at each of the different storage servers: i) incorporating the received one of the multiple data fragments and one or more parity fragments into an extent comprising multiple fragments of other objects; ii) performing a second error correction encoding process on multiple extents including the extent to generate parity information for the multiple extents; and, iii) storing the multiple extents and the parity information.

Abstract: Described technologies extend the information available from an execution trace of a program by providing heuristically-derived values for memory contents when the trace does not include data expressly showing the value of a memory cell at a particular execution time. Various heuristics are described. The heuristics may use information about the memory cell at other times to produce the derived value. Some heuristics use other trace data, such as whether the memory cell is in a stack, whether there are gaps in the trace, or whether garbage collection or compilation occurred near the time in question. Grounds for the derived value are reported along with the derived value. A time-travel debugger or other program analysis tool can then present the derived values to users, or make other use of the derived values and grounds to assist debugging and other efforts to improve the functioning of a computing system.

Abstract: Methods of operating apparatus include receiving user data for programming to a grouping of memory cells of the apparatus, associating an address of the grouping of memory cells with the user data, determining whether power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, and if power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, programming the address of the grouping of memory cells to a different grouping of memory cells of the apparatus. Methods of operating apparatus further include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.

Abstract: A method for execution by a computing device includes generating a data segment to include a first data object for storage and a plurality of null data objects. The data segment is dispersed storage error encoded to produce a set of encoded data slices that includes a first encoded data slice that corresponds to the first data object, a plurality of null slices corresponding to the null data objects, and a remaining number of error coded slices. Storage of the set of encoded data slices in a set of storage units is facilitated. Storage of a second data object is facilitated, where one null data object is overwritten with the second data object. A partial contribution of the second data object is calculated for each of the error coded slices in accordance with a partial encoding approach. Each error coded slice is updated by utilizing the corresponding partial contribution.

Abstract: A method for execution by a computing device includes dispersed storage error encoding a data segment to produce a set of encoded data slices in accordance with an information dispersal algorithm (IDA) width number. Storage of the set of encoded data slices in a set of storage units is maintained. Activation of an incremental subset of storage units is detected to produce an expanded set of storage units in accordance with an updated IDA width number. An incremental subset of encoded data slices of an expanded set of encoded data slices is generated in accordance with the updated IDA width number. Storage of the expanded set of encoded data slices in the expanded set of storage units is maintained. A write threshold number is updated to produce an updated write threshold number. Storage of the updated write threshold number of the expanded set of encoded data slices is maintained.

Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes receiving data for storage. A storage approach for the data is determined based on the data. Storage of the data in a plurality of sets of storage units is facilitated in accordance with the storage approach. A determination is made to recover the data from storage, and a set of storage units is selected from the plurality of sets of storage units for recovery of the data. Recovery of the data from the selected set of storage units is facilitated.