Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

Abstract: A memory system includes: a memory device including a plurality of memory blocks each having a plurality of pages suitable for storing data; and a controller suitable for: receiving a plurality of commands from a host; controlling the memory device to perform a plurality of command operations in response to the plurality of commands; identifying parameters for the memory blocks affected by the command operations performed to the memory blocks; selecting first memory blocks among the memory blocks according to the parameters; and controlling the memory device to swap data stored in the first memory blocks to second memory blocks among the memory blocks.

Abstract: A storage control device operable to be one of a plurality of storage control devices included in a storage device, the storage control device includes: a memory; and a processor coupled to the memory, the processor being configured to processing, the processing including: executing a determination processing that includes determining whether activation of the storage control device is caused by activation of the entire storage device or activation of the storage control device alone; and executing a region setting processing that includes setting a control information storage region that stores control information used to enable a function of the storage device according to a determination result by the determination processing.

Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.

Abstract: Provided herein are systems, methods and computer readable media for providing an out of band cache mechanism for ensuring availability of data. An example system may include a client device configured to, in response to determining requested data is not available in a cache, access the requested data from a data source, transmit, to a cache mechanism, an indication that the requested data is unavailable in the cache, the indication configured to be placed in a queue as an element pointing to the requested data, a cache mechanism configured to receive an indication of requested data, determine whether an element, the element indicative of the requested data, exists in a queue, and in an instance in which the element is not present in the queue, placing the element in the queue, the queue being a list of elements, each indicative of requested data needing to be placed in the cache.

Abstract: A memory system includes: a first memory subsystem suitable for storing a first segment of map data for first logical addresses in a logical address region; a second memory subsystem suitable for storing a second segment of map data for second logical addresses in the logical address region; and a host interface suitable for: providing any one of the first and second memory subsystems with a first read command of a host according to a logical address included in the read command, providing the host with an activation recommendation according to a read count of the logical address region including the provided logical address, providing map data for the first and second logical addresses obtained from the first and second memory subsystems, wherein the activation recommendation allows the host to further provide a physical address corresponding to a target logical address in the logical address region.

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.

Abstract: A virtual storage device may be generated that replicates a layout of a physical storage device it is replacing. The virtual storage device may be used to store data formerly stored in the physical storage device. The layout may detail various configurations of the physical storage device such as if the physical storage derive implements fixed or variable-block sizes and/or if it implements a level of redundant array of independent disks (RAID). By replicating the layout of a physical storage device that it may replace, the virtual storage device described within various embodiments may offer advantages over other virtual storage devices.

Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.

Abstract: Apparatus and method for object storage, such as a solid-state drive (SSD) or array thereof. In some embodiments, data arranged as an object are presented for storage to a non-volatile memory (NVM) of a data storage device. Prior to storage, a configuration of the NVM is adaptively adjusted, such as by adjusting a garbage collection unit (GCU) layout, an error correction code (ECC) scheme, and/or a map metadata format used by the NVM. The object is thereafter stored to the NVM using the adaptively adjusted configuration. A controller of the data storage device generates a predicted remaining storage capacity of the NVM in terms of additional objects that can be stored by the NVM responsive to the adaptively adjusted configuration of the NVM. A non-linear sliding scale may be used such that a greater number of smaller objects or a smaller number of larger objects may be accommodated.

Abstract: A technique for oblivious filtering may include receiving an input data stream having a plurality of input elements. For each of the input elements received, a determination is made as to whether the input element satisfies a filtering condition. For each of the input elements received that satisfies the filtering condition, a write operation is performed to store the input element in a memory subsystem. For those of the input elements received that do not satisfy the filtering condition, at least a dummy write operation is performed on the memory subsystem. The contents of the memory subsystem can be evicted to an output data stream when the memory subsystem is full. The memory subsystem may include a trusted memory and an unprotected memory.

Abstract: An operating method of a memory system includes determining that a map management operation is triggered, based on physical-to-logical (P2L) entries generated after a previous map management operation is completed, wherein the P2L entries respectively correspond to physical addresses of a memory region of a storage medium; generating a pre-update table corresponding to the memory region based on the P2L entries regardless of whether a write operation of the storage medium is completed; updating L2P entries based on the P2L entries after the write operation is completed; and generating, a new original update table by merging the pre-update table and an original update table corresponding to the memory region when the original update table is present in the storage medium and generating, after the L2P entries are updated, the pre-update table as the new original update table when the original update table is not present in the storage medium.

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

Abstract: A directory processing method and apparatus are provided to resolve a problem that a directory occupies a relatively large quantity of caches in an existing directory processing solution. The method includes: receiving, by a first data node, a first request sent by a second data node; searching for, by the first data node, a matched directory entry in a directory of the first data node based on tag information and index information in a first physical address; creating, when no matched directory entry is found, a first directory entry of the directory based on the first request, where the first directory entry includes the tag information, first indication information, first pointer information, and first status information, the first pointer information is used to indicate that data in the memory address corresponding to the indication bit that is set to valid is read by the second data node.

Abstract: A method for demoting a selected storage element from a cache memory includes storing favored and non-favored storage elements within a higher performance portion and lower performance portion of the cache memory. The method maintains a plurality of favored LRU lists and a non-favored LRU list for the higher and lower performance portions of the cache memory. Each favored LRU list contains entries associated with the favored storage elements that have the same unique residency multiplier. The non-favored LRU list includes entries associated with the non-favored storage elements. The method demotes a selected favored or non-favored storage element from the higher and lower performance portions of the cache memory according to a cache demotion policy that provides a preference to favored storage elements over non-favored storage elements based on a computed cache life expectancy, residency time, and the unique residency multiplier.

Abstract: A method for managing a data cache, comprising: storing a cache management list comprising a plurality of entries and having: a tail part stored in a first storage and documenting recently accessed data items stored in the data cache, a body part stored in a second storage and documenting less recently accessed data items stored in the data cache, and a head part stored in the first storage and documenting least recently accessed data items stored in the data cache; and in each of a plurality of iterations: receiving at least one data access request; documenting the data access request in the tail; identifying a plurality of duplicated entries present in the body and the tail; and removing each of the plurality of duplicated entries from the body in the second storage according to a physical organization in the second storage of the plurality of duplicated entries.

Abstract: According to one embodiment, a storage device is configured to store unencrypted user data. The user data is erased according to at least one data erasure mechanism. The storage device comprises a receiver configured to receive an inquiry from a host device, and a transmitter configured to transfer response information indicating the at least one data erasure mechanism to the host device.

Abstract: A cryptographic accelerator may include an input buffer to store first data, including a first portion of a message, in a first address range and second data, including a second portion of the message, in a second address range. The cryptographic accelerator may include one or more components to determine lengths of the first and second portions, read the first portion from the first address range, discard any dummy data in the first address range based on an indication of an endpoint of the first data in the first address range, read the second portion from the second address range, and discard any dummy data in the second address range based on an indication of an endpoint of the second data in the second address range. The cryptographic accelerator may include a cryptographic engine to perform a cryptographic operation using the first portion and the second portion.

Abstract: An indication that a secondary storage system is offline is received. A cloud instantiation of the secondary storage system is generated. Generating the cloud instantiation of the secondary storage system comprises virtually rebuilding one or more secondary storage clusters of the secondary storage system including by reconstituting a tree data structure of the secondary storage system in the cloud instantiation of the secondary storage system based on serialized data included in a snapshot archive. The reconstituted tree data structure is comprised of at least a root node and one or more nodes storing data. The serialized data is comprised of a flat set of data blocks. Each data block included in the flat set of data blocks corresponds to one of a plurality of nodes of a tree data structure. The tree data structure is comprised of at least the root node and the one or more nodes storing data.