Abstract: According to one embodiment, a storage device is configured to store unencrypted user data. The user data is erased according to at least one data erasure mechanism. The storage device comprises a receiver configured to receive an inquiry from a host device, and a transmitter configured to transfer response information indicating the at least one data erasure mechanism to the host device.

Abstract: A cryptographic accelerator may include an input buffer to store first data, including a first portion of a message, in a first address range and second data, including a second portion of the message, in a second address range. The cryptographic accelerator may include one or more components to determine lengths of the first and second portions, read the first portion from the first address range, discard any dummy data in the first address range based on an indication of an endpoint of the first data in the first address range, read the second portion from the second address range, and discard any dummy data in the second address range based on an indication of an endpoint of the second data in the second address range. The cryptographic accelerator may include a cryptographic engine to perform a cryptographic operation using the first portion and the second portion.

Abstract: An indication that a secondary storage system is offline is received. A cloud instantiation of the secondary storage system is generated. Generating the cloud instantiation of the secondary storage system comprises virtually rebuilding one or more secondary storage clusters of the secondary storage system including by reconstituting a tree data structure of the secondary storage system in the cloud instantiation of the secondary storage system based on serialized data included in a snapshot archive. The reconstituted tree data structure is comprised of at least a root node and one or more nodes storing data. The serialized data is comprised of a flat set of data blocks. Each data block included in the flat set of data blocks corresponds to one of a plurality of nodes of a tree data structure. The tree data structure is comprised of at least the root node and the one or more nodes storing data.

Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.

Abstract: Provided are a computer program product, system, and method for reducing a rate at which data is mirrored from a primary server to a secondary server. A determination is made as to whether a processor utilization at a processor managing access to the secondary storage exceeds a utilization threshold. If so, a determination is made as to whether a specified operation at the processor is in progress. A message is sent to the primary server to cause the primary server to reduce a rate at which data is mirrored from the primary server to the secondary server in response to determining that the specified operation is in progress.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Abstract: Method, system, and computer program product for dynamic address translation for a virtual machine are disclosed. The method includes obtaining a memory portion from a memory space, in response to a request for building a shadow dynamic address translation table, wherein the memory space is allocated for at least one guest operation system and wherein the shadow dynamic address translation table includes a mapping between at least one guest logic memory address and at least one host physical memory address. The method further includes building the shadow dynamic address translation table and storing the shadow dynamic address translation table in the memory portion.

Abstract: A method is described that includes generating, by a controller of a storage device, operating statistics associated with an operating state of the storage device. The method includes receiving, by the controller and from a host device, a non-interrupt command frame that requests transfer of data blocks between the storage device and the host device. The method further includes, in response to receiving the non-interrupt command frame, generating, by the controller, a response frame associated with the non-interrupt command frame, wherein the response frame includes the operating statistics. The method includes transmitting, by the controller and to the host device, the response frame.

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

Abstract: In one embodiments, one or more first computing devices receive updated values for user data associated with a plurality of users; and for each of the user data for which an updated value has been received, determine one or more second systems that each have subscribed to be notified when the value of the user datum is updated and each have a pre-established relationship with the user associated with the user datum; and push notifications to the second systems indicating that the value of the user datum has been updated without providing the updated value for the user datum to the second systems.

Abstract: Methods, computer media encoding instructions, and systems that receive write requests directed to non-sequential logical block addresses and write the write requests to sequential disk block addresses in a storage system include an overprovision of a storage system to include an increment of additional storage space such that it is more likely a large enough sequential block of storage will be available to accommodate incoming write requests.

Abstract: Systems and procedures are provided to enable fixed block architecture (FBA) device support over fiber connections using transport mode protocol. The FBA devices may have a size greater than 2 terabytes. The system may be used with existing fixed block command sets according to the transport mode protocol. The existing fixed block command sets may be extended to permit addressing of greater than 2 terabytes. The transport mode protocol may be based on a high performance protocol implementation that facilitates processing of I/O requests.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: Provided are a computer program product, system, and method for using inactive copy relationships to resynchronize data between storages. A first and second groups of active copy relationships are established to serially copy data among the storages in the first and second groups, respectively. At least one of the storages in both the first group and the second group comprise overlapping storages that are members of both the first and second groups and at least one of the storages in both the first and second groups comprise non-overlapping storages that are a member of only one of the first and second groups. At least one inactive copy relationship is established having as a source storage one of the non-overlapping storages in the first group and as a target storage one of the non-overlapping storages in the second group.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: A processor issues a command to a memory through an electrical memory link and performs a process according to the command through the electrical memory link. The processor issues a routing command to an optical circuit switch (OCS) through an OCS control line. In response to the routing command, the OCS establishes a routing of an optical memory link from the processor to the BDM. In response to the establishment of the optical memory link from the processor to the BDM, the processor (or a BDM (internal/dedicated) controller) switches from performing the process through the electrical memory link to performing a process through the optical memory link (continuously without an interruption between the successive processes). Corresponding systems are also disclosed herein.

Abstract: A memory system and method for delta writes are provided. In one embodiment, a memory system receives a request to store data in the memory and determines whether the data requested to be stored in the memory is a modified version of data already stored in the memory. If it is, the memory system compares the data requested to be stored in the memory with the data already stored in the memory to identify differences between the data to be stored and the data already stored. The memory system then stores the identified differences in the memory, along with a table that maps the stored identified differences to corresponding locations in the data already stored in the memory. Other embodiments are provided.