Abstract: One embodiment provides a method that includes displaying Boolean combinations of two or more bit planes.

Abstract: An input system comprising a computer operably associated with a display screen, a first input device, and a second input device. The first input device has an operating region corresponding to an operation region displayed on the display screen. The operation region may be enlarged, reduced, or moved in response to an operation of the second input device.

Abstract: A projection system for displaying an arbitrary combination of superimposed and tiled images using a plurality of projectors. A sub-frame generator generates a plurality of sub-frames corresponding to an image frame for simultaneous display by the projectors in at least partially overlapping positions on a display surface. The sub-frames are generated using optimal sub-pixel blending maps that are derived by forming a simulated image to approximate a target image subject to at least one smoothing constraint between the simulated image and the target image. The target image is formed from the image frame using at least one property (e.g., luminance or color) of each of the plurality of projectors.

Abstract: A method is provided for creating a quadrant array by using two consecutive points in an array of x, y coordinate values generated by movements of a computer mouse or a digitizer tablet. The quadrant array is then saved in computer storage for later verification with a sample quadrant array by using a comparison function.

Abstract: A plasma display apparatus includes a plasma display panel, a chassis base having a first surface to which the plasma display panel is attached and a second surface on which a driving circuit module is installed, and at least one gripper provided on the second surface of the chassis base, the gripper being integrally formed with the chassis base, the gripper being protruded with respect to the second surface of the chassis base. A technique of manufacturing a chassis base for a plasma display apparatus, includes applying a press working process to a chassis base body to provide a chassis base, forming a pair of parallel incision lines on the chassis base, and pressing a portion partitioned by the incision lines toward a thickness direction of the chassis base to form a grip body.

Abstract: An Electron Emission Display (EED) device, adapted to of adjust a pulse width of data signal according to an active pulse width of a horizontal synchronization signal, includes: a scan driver, a data driver; an EED panel displaying display data; a reference signal memory adapted to store a lookup table of active pulse widths of horizontal synchronization signals defined by a system clock and reference signals corresponding to the active pulse widths of the horizontal synchronization signals; a reference signal referring unit adapted to output a reference signal in accordance with the lookup table stored in the reference signal memory; and a gray level signal generator adapted to count the reference signal and output a gray level signal to the data driver, the data driver outputting video data corresponding to the gray level signal to data electrode lines of the EED panel.

Abstract: A plurality of pairs of switch parts and current source circuits are disposed in each pixel. Switching of each of a plurality of the switch parts is controlled by a digital video signal. When the switch part is turned on, by a current supplied from the current source circuit making a pair with the switch part, the light emitting element emits light. A current which is supplied from one current source circuit to the light emitting element is constant. A value of a current flowing through the light emitting element is comparable to a value of added currents which are supplied to the light emitting element from respective all current source circuits making pairs with the switch parts which are in the conductive states.

Abstract: A display device in accordance with the present invention changes to Vc the voltage of a terminal of a capacitor C2 the other terminal of which is connected to the gate of a driver TFT Q1. Thus, a desired voltage Vda is fed from a source line Sj to the drain of the driver TFT Q1 so as to adjust the threshold voltage Vth of the driver TFT Q1. The device then changes the voltage of the terminal of the capacitor C2 to Va to render the gate voltage of the driver TFT Q1 Vda-Vth-Vc+Va. A power supply voltage Vp is fed from the source of the driver TFT Q1.

Abstract: Writing of a digital video signal of a lower order bit into a memory is eliminated during a second display mode in which the number of gradations is reduced as compared to in a first display mode of high-level gradation. In addition, read out of the digital video signal of the lower order bit from the memory is also eliminated. The amount of information of a digital image signal inputted to a source signal line driver circuit is reduced. In accordance with such operation, a display controller functions to make start pulses and clock pulses inputted to the source signal line driver circuit have a lower frequency and to lower a driving voltage. When the gradation is reduced, a frame period in the second display mode may be set longer as compared to that in the first display mode, and therefore low electric power consumption is achieved.

Abstract: A system for calibrating a display device to improve its perceived image quality includes a calibration module configured to determine, for each of a plurality of white colors associated with a plurality of gray levels, a measured chromaticity point on a chromaticity diagram and a measured luminance level. The calibration module calculates, for each gray level, a differential change in each primary color component that simultaneously moves the measured chromaticity point to a target chromaticity point and adjusts the measured luminance level to a target luminance level on a predetermined luminance curve having a target gamma value, and calculates correction values for each primary color component and each gray level based on the calculated differential changes. The system also includes means for outputting the calculated correction values to the display device, which corrects the primary color components of a color video signal based on the calculated correction values.

Abstract: Disclosed is a PDP driving method having a misfiring erase period between reset and address periods. Large amounts of positive and negative charges are respectively formed on scan and sustain electrodes because of an unstable reset operation in the reset period. Because of the charges, discharging can occur between the scan and sustain electrodes in the sustain period even without addressing in the address period. In the misfiring erase period, a voltage is applied between the scan and sustain electrodes to generate discharging and respectively form negative and positive charges on the scan and sustain electrodes. An erase pulse is then applied to erase the negative and positive charges respectively formed on the scan and sustain electrodes.

Abstract: A display device capable of applying reverse driving voltage for a light emitting element to a light emitting element every certain period for prolonging light emitting element's life and burning out a shorted portion. Besides a path for supplying forward current to the light emitting element, a path for supplying reverse current is provided. A driving transistor is provided in the former path while a transistor (AC transistor) is provided in the latter path, thereby a switching between the two paths is controlled. The AC transistor has a rate L/W of a channel length L to a channel width W smaller than that of the driving transistor. Accordingly, current flowing into the light emitting element can flow into the AC transistor in the case of reverse driving voltage being applied to the light emitting element.

Abstract: A display device, where the power consumption of a display panel can be reduced by controlling a display time rate, including an average gray scale calculator obtaining an average gray scale by averaging a gray scale of each pixel over an entire screen of one frame and for outputting an average gray scale signal, a display time rate table outputting a magnification signal for reducing the display time rate when the average gray scale exceeds a certain value in accordance with the average gray scale signal, and a timing signal generator generating an erase start signal for erasing the digital video signal written to the each pixel in accordance with the magnification signal.

Abstract: An apparatus which comprises a manipulandum that is configured as a surgical instrument; a closed loop linkage system which includes a first central member fixedly coupled to a first object coupling and a second central member fixedly coupled to a second object coupling, wherein the first and second object couplings are separately coupled to the manipulandum to allow the manipulandum to be moveable in a plurality of rotary degrees of freedom and an axial degree of freedom; a force feedback system is coupled to the linkage system, wherein the force feedback system selectively applies resistive forces to the manipulandum based on the position of the manipulandum with respect to one or more reference coordinates. In an embodiment, the force feedback system includes an actuator to provide a force to the manipulandum in at least one degree of freedom in response to signals received from a computer system.

Abstract: A system for implementing personal video recording, in which integrated drive electronics are incorporated in set-top box logic, instead of with a hard disk drive. This allows the set-top box logic to communicate directly to the hard disk, so that no intervening bus is necessary.

Abstract: When an input detection unit has detected that no user operation has been performed to an organic EL display apparatus for a predetermined period of time or when a processing detection unit has detected that a predetermined processing is being performed, the input detection unit or the processing detection unit outputs an instruction to a reference voltage adjusting unit to modify a reference voltage referenced by a DAC unit upon conversion to an analog output signal.

Abstract: A joystick device is provided that is in electronic communication with a remotely located main electronic controller used to control heavy machinery and the like. The joystick device includes a base assembly having a first microprocessor in electronic communication with the main electronic controller. The joystick device also includes a grip assembly pivotally connected to the base assembly. The grip assembly includes a plurality of input buttons and a second microprocessor in electronic communication with the first microprocessor. The joystick device further includes sensing elements that detect movement of the joystick device.

Abstract: An electro-optic display is driven using a plurality of different drive schemes. The waveforms of the drive schemes are chosen such that the absolute value of the net impulse applied to a pixel for all homogeneous and heterogeneous irreducible loops divided by the number of transitions in the loop is less than about 20 percent of the characteristic impulse (i.e., the average of the absolute values of the impulses required to drive a pixel between its two extreme optical states).

Abstract: A plasma display panel and an imaging device realize a high luminous efficiency, a long lifetime and stable driving. The plasma display panel uses a discharge-gas mixture containing at least Xe, Ne and He. A Xe proportion of the discharge-gas mixture is in a range of from 2% to 20%, a He proportion of the discharge-gas mixture is in a range of from 15% to 50%, the He proportion is greater than the Xe proportion, and a total pressure of the discharge-gas mixture is in a range of from 400 Torr to 550 Torr. A width of a voltage pulse to be applied to an electrode serving as an address electrode is 2 ?s or less.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. A system and method for displaying an analog source image by a digital display unit. A converter circuit generates a plurality of digital source image elements from an analog source image based upon a sampling clock signal synchronized with a time reference signal associated with the analog source image.