Abstract: An output circuit includes a comparator circuit, a voltage conversion circuit and a signal output circuit. The comparator circuit detects an operating mode based on a first supply voltage and a second supply voltage and generates a first control signal. The voltage conversion circuit adjusts a level of an output voltage from a low-dropout regulator according to the first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. The signal output circuit adjusts a level of a digital signal according to the first voltage, the second voltage and the first supply voltage to generate a digital output signal corresponding to the operating mode.

Abstract: In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.

Abstract: A comparator circuit, including an input circuit, first and second inverting amplification circuits, first and second coupling circuits, and a feedback circuit, wherein the input circuit generates an amplified input signal based on positive and negative input voltages, the first inverting amplification circuit generates an intermediate amplified signal based on the amplified input signal during a sampling period, the second inverting amplification circuit generates a comparison result signal based on the intermediate amplified signal during the sampling period, the first coupling circuit is connected between the input circuit and the first inverting amplification circuit, the second coupling circuit is connected between the first inverting amplification circuit and the second inverting amplification circuit, and the feedback circuit amplifies the input node of the first inverting amplification circuit with a rail-to-rail voltage corresponding to a power supply voltage or a ground voltage based on the comparis

Abstract: Devices and methods for operating a charge pump. In some implementations, a charge pump module includes a clock circuit configured generate to a first clock signal and a second clock signal, the first clock signal having a lower frequency than the second clock signal. The charge pump module also includes a driving circuit configured to generate a first set of clock signals based on the first clock signal and a second set of clock signals based on the second clock signal, the driving circuit coupled to the clock circuit. The charge pump module further includes a charge pump core including a set of capacitances, the charge pump core configured to charge the set of capacitances based the first set of clock signals and the second set of clock signals.

Abstract: A multi-antenna system for harvesting energy and transmitting data includes an energy storing unit, antenna transmission units, and a load unit. Each antenna transmission unit includes an antenna module, a splitting module, an energy generation module, and a data processing module. The splitting module splits a wireless signal received by the antenna module into a first splitting signal and a second splitting signal and transmits the first splitting signal to an energy generation module to convert the first splitting signal into electrical energy stored in an energy storing unit and provided to the data processing module. The energy storing unit provides the electrical energy for the load unit. The data processing module receives one of the second splitting signals, converts it into a control signal, and transmits the control signal to the load unit. The load unit operates according to the control signal.

Abstract: Embodiments relate to an amplifier circuit. The amplifier circuit includes multiple transistors. Each transistor is configured to receive an input signal and output an amplified signal. The amplifier circuit additionally includes a set of input chopper circuits and a set of output chopper circuits. Each output chopper circuit corresponds to one input chopper of the set of input choppers. Each input chopper circuit and its corresponding output chopper are controlled by one or more control signals from a set of control signals. Each input chopper circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal or a second input terminal based on a value of the one or more control signals. Moreover, each output chopper circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal or a second output terminal based on the value of the one or more control signals.

Abstract: A packaged acoustic wave filter component can include an acoustic wave device including a first piezoelectric layer and an interdigital transducer electrode on the first piezoelectric layer. A support layer may be included over the acoustic wave device, and the packaged hybrid filter component can also include a bulk acoustic wave resonator over the support layer. A cap layer may extend over and encapsulate the bulk acoustic wave resonator. One or more external vias may extend through the support layer and the underlying layers of the acoustic wave device to provide electrical communication with the packaged bulk acoustic wave generator.

Abstract: An acoustic wave filter component can include a surface acoustic wave device including a first piezoelectric layer, an interdigital transducer electrode on the first piezoelectric layer, and an additional layer, such as a temperature compensation layer, over the interdigital transducer electrode. The acoustic wave filter component can also include a bulk acoustic wave resonator supported by the additional layer. The additional layer may be a layer on which a surface acoustic wave of the surface acoustic wave device will propagate. The bulk acoustic wave resonator may include an air cavity, where a shape of the air cavity is defined in part by the additional layer.

Abstract: The present invention discloses a comparison circuit having adaptive comparison mechanism is provided. A comparator is enabled by an enabling signal having an enabling state during a comparison stage to compare a first voltage and a second voltage to generate a comparison result. A comparison determining circuit sets a stage indication signal at an unfinished state and a finished state before and after the comparison result is generated. A time accumulating circuit starts to accumulate an accumulated time when the enabling signal is at the enabling state and stops accumulating when the stage indication signal is at the finished state to generate a comparison time. A determining circuit performs statistics on the comparison time to generate a predetermined threshold time and sets a predetermined comparison result as the comparison result under the condition that the comparison result is not generated and the accumulated time exceeds the predetermined threshold time.

Abstract: This disclosure provides systems, methods, and apparatus, including computer programs encoded on computer-readable media, for implementing a power harvesting protocol at a network entity and a channel engineering device (CED) of a wireless communication network. In some aspects, the network entity and the CED may implement a power harvesting protocol that includes power harvesting capabilities and configuration signaling to support power harvesting at the CED. The CED may provide a power harvesting capabilities message to the network entity that includes a parameter that indicates capabilities for power harvesting at the CED. The network entity may respond with a power harvesting configuration message to configure the CED for power harvesting. After configuration of the CED, the network entity may transmit dedicated and non-dedicated (or opportunistic) power harvesting signals to the CED for use by the CED for power harvesting.

Abstract: A level shift circuit includes first to fourth n-type transistors, first and second p-type transistors, and first and second inverters. The first n-type transistor receives an input signal at its gate and has a drain connected to an inverted output node. The first p-type transistor is placed between a third power supply and the inverted output node. The second n-type transistor receives an inverted input signal at its gate and has a drain connected to an output node. The second p-type transistor is placed between the third power supply and the output node. The third n-type transistor is between the inverted output node and an inverted input node, and the first inverter between the drain and gate of the third n-type transistor. The fourth n-type transistor is between the output node and an input node, and the second inverter between the drain and gate of the fourth n-type transistor.

Abstract: The invention relates to a device for controlling a plurality of semiconductor circuit breakers by means of driver voltages for the synchronous operation of a plurality of loads in the high-voltage range, where the driver voltages can be provided by a transformer. According to the invention, the driver voltages for the semiconductor circuit breakers are tapped from a single secondary winding of the transformer, where electronic voltage level converter circuits are provided to obtain the driver voltages from the secondary winding of the transformer at the required magnitude.

Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.

Abstract: Aspects of this disclosure relate to a surface acoustic wave device with a vertical stack over a piezoelectric layer. The vertical stack can include a first acoustic reflector disposed on the piezoelectric layer, a second acoustic reflector disposed on the piezoelectric layer, and an interdigital transducer electrode disposed on the piezoelectric layer and positioned between the first acoustic reflector and the second acoustic reflector. The interdigital transducer electrode has a first side that is closer to the first acoustic reflector and a second side that is closer to the second acoustic reflector. A vertical arrangement of the vertical stack can be configured such that an acoustic wave propagation velocity of a first region between the first side and a first reflector is faster than an acoustic wave propagation velocity of a second region between the first side and the second side.

Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.

Abstract: An acoustic wave device includes first and second acoustic wave elements. The first acoustic wave element is disposed on a piezoelectric substrate, and includes at least one first IDT electrode. The second acoustic wave element is disposed on the piezoelectric substrate, and includes at least one second IDT electrode. The first and second acoustic wave elements are adjacent to each other in the direction of acoustic wave propagation. A diffracting component that diffracts an acoustic wave is disposed between the first IDT electrode and the second IDT electrode. The diffracting component includes a gap that defines and functions as a slit to diffract an acoustic wave.

Abstract: A flip-flop circuit includes a first master latch circuit transmitting an inverted signal of an input signal received from an external device to a first node and transmitting an inverted signal of a signal of the first node to a second node, according to a first control signal having a first logic level or a second control signal having a second logic level, a first slave latch circuit transmitting an inverted signal of a signal of the second node to a third node according to the first control signal having the second logic level or the second control signal having the first logic level, a first output inverter generating a first output signal by inverting a signal of the third node, and a first control signal generation circuit generating the first control signal and the second control signal based on a clock signal and the signal of the first node.

Abstract: A safety interlock system includes a safety harness comprising a plurality of buckles to secure the harness to a user and a safety attachment ring. A fall-arrest belt clip is configured to be releasably attached to the safety attachment ring, the fall-arrest belt clip attached to a fall-arrest tether of a machine. The system further includes a safety interlock means for disabling an operation of the machine when the fall-arrest clip is detached from the safety attachment ring, the machine coupled to the fall-arrest tether.

Abstract: In an embodiment, a phase change switch device is provided. The phase change switch includes a phase change material, a set of heaters arranged to heat the phase change material and a power source. A switch arrangement including a plurality of switches is provided, which is configured to selectively provide electrical power from the power source to the set of the heaters.

Abstract: A slew rate control device and a slew rate control method are provided. The slew rate control device includes a signal generating circuit, a comparator circuit, and a control circuit. The signal generating circuit generates a first voltage signal and a second voltage signal having a slew rate, and the first voltage signal and the second voltage signal are a pair of differential signals. The comparator circuit outputs an enabling signal according to a relative positional relationship between an eye crossing point of the pair of differential signals and a signal edge of a reference clock. The control circuit generates at least one control signal according to the enabling signal to control the signal generating circuit, such that the signal generating circuit changes the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal.