Abstract: According to one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first end, a second end, and a first body. The second transistor includes a third end coupled to the second end, a fourth end, and a second body. The semiconductor device includes a first resistor coupled to the first end, a second resistor coupled between the first resistor and the second end, a third resistor coupled to the third end, a fourth resistor coupled between the third resistor and the fourth end, a first diode coupled between the first body and a node coupling the third resistor and the fourth resistor, and a second diode coupled between the second body and a node coupling the first resistor and the second resistor.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.

Abstract: A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.

Abstract: A signal receiver adaptive to a noise level includes a first comparator, a second comparator, a control unit, and a reference voltage changing unit. The first comparator compares a voltage of a received signal with a first reference voltage, and the second comparator compares the voltage of the received signal with a second reference voltage. The control unit outputs a control voltage having a voltage level corresponding to the number of output pulses per unit time of the first comparator. The reference voltage changing unit changes the magnitudes of the first reference voltage and the second reference voltage in response to a voltage level of a control voltage. The second comparator compares the changed second reference voltage with the received signal to output a transmission signal from which noise is cancelled. A voltage level of noise to be cancelled from the received signal varies according to a noise level, so the noise cancellation adaptive to the noise level is performed.

Abstract: A pulse generator and a method for generating pulses are provided. The pulse generator includes at least one first transmission line with a first and a second end; at least one second transmission line with a first and a second end; a voltage source; a switching unit; and a charge control device. The charge control device is adapted to connect an output of the voltage source to the first end of the at least one first transmission line. A first switch S1 in the switching unit is adapted to connect or disconnect the second end of the at least one first transmission line to the first end of the at least one second transmission line for predetermined time spans. A second switch S2 in the switching unit is adapted to connect or disconnect the first end of the at least one second transmission line to a fixed potential. The opening or closing states of S1 and S2 in the switching unit are mutually exclusive. A second end of the at least one second transmission line is adapted to be connected to a load.

Abstract: A bidirectional RF circuit, preferably including a plurality of terminals, a switch, a transistor, a coupler, and a feedback network. The circuit can optionally include a drain matching network, an input matching network, and/or one or more tuning inputs. In some variations, the circuit can optionally include one or more impedance networks, such as an impedance network used in place of the feedback network; in some such variations, the circuit may not include a coupler, switch, and/or input matching network. A method for circuit operation, preferably including operating in an amplifier mode, operating in a rectifier mode, and/or transitioning between operation modes.

Abstract: A multiple functioning superconductive device was invented based on Toroidal Josephson Junction (FFTJJ) array with 3D-cage structure self-assembled organo-metallic superlattice membrane. The device not only mimics the structure and function of an activated Matrix Metalloproteinase-2 (MMP-2) protein, but also mimics the cylinder structure of the Heat Shock Protein (HSP60) protein, that works at room temperature under a normal atmosphere, and without external electromagnetic power applied. The device enabled direct rapid real-time monitoring atto-molarity concentration ATP in biological specimens and was able to define the anti-inflammatory and pro-inflammatory status revealed a transitional range of ATP concentration under antibody-free, tracer-free and label-free conditions.

Abstract: A footwear system includes a sensorized insole and a charger. The sensorized insole has an insole bulk having a foot-facing upper surface. A sensor is embedded in the insole bulk for measuring a parameter of a user's foot, a battery is embedded in the insole bulk for providing energy to the sensor, and a receiver pod is embedded in the insole bulk and is spaced from the foot-facing upper surface for wirelessly receiving energy and providing energy to the battery. The charger provides energy to the receiver pod, and includes a cable for connecting to an energy source, and a transmitter pod electrically connected to the cable for receiving energy from the cable and wirelessly transmitting energy to the receiver pod. The transmitter pod is positionable against the foot-facing upper surface to wirelessly provide energy to the receiver pod through the insole bulk.

Abstract: A stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element. The second layer element includes side by side first and second wire components in parallel spaced relation extending around the center axis and the first wire component is connected to the first layer wire element to form a primary turn winding. A third layer includes a third layer wire element extending around the center axis and connected to the second wire component of the second layer wire element to form a secondary turn winding partially overlapping with the primary turn winding.

Abstract: A relay circuit, including a solid state relay switch, connected to a first relay line and to a charging capacitor, and connected to a second relay line. The relay circuit may also include a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may include a voltage detection circuit, having an input coupled to an output of the charging capacitor, and having an output arranged to generate a LOW voltage signal when a voltage level of the charging capacitor is below a low threshold value. The solid state relay control circuit may also include a zero crossing circuit, coupled to the first relay line and the second relay line, and having an output to generate a clock signal when a zero crossing event takes place between the first relay line and the second relay line.

Abstract: Distributing higher currents demanded by a power consuming load(s) exceeding overcurrent limits of a current limiter circuit for a power source in a power distribution system. The power distribution system receives and distributes power from the power source to a power consuming load(s). The power distribution circuit is configured to limit current demand on the power source to not exceed a designed source current threshold limit. The power distribution circuit includes an energy storage circuit. The power distribution circuit is configured to charge the energy storage circuit with current supplied by the power source. Current demanded by the power consuming load(s) exceeding the source current threshold limit of the power source is supplied by the energy storage circuit. Thus, limiting current of the power source while supplying higher currents demanded by power consuming load(s) exceeding the source current limits of the power source can both be accomplished.

Abstract: An energy harvester and a method for tuning an antenna frequency of the energy harvester is provided. The energy harvester includes: a tuner circuit coupled to at least one antenna, wherein the tuner circuit includes at least one adjustable capacitor, wherein the at least one antenna is configured to harvest an electromagnetic ambient energy; a controller connected to the tuner circuit, wherein the controller is configured to control a voltage level within the energy harvester, wherein the controller is configured to iteratively set the at least one adjustable capacitor to tuning states until a best tuning state is set, wherein the best tuning state of the at least one adjustable capacitor substantially matches an antenna frequency and a frequency of the electromagnetic ambient energy; and a rectifier to convert the electromagnetic ambient energy to a direct current.

Abstract: A voltage generating circuit includes a first transistor and a second transistor. Voltage of a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the voltage generating circuit. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as an output of the voltage generating circuit. A gate of the second transistor is connected to a drain of the second transistor.

Abstract: A timing generator includes a first current source, a first switch, a second current source, a second switch, a third switch, a capacitor, a signal synthesizer, and a timing difference extractor. The first current source is for generating a first current according to the input voltage. The second current source is for generating a second current according to the input voltage. The first switch includes a control terminal for receiving a charging signal. The second switch includes a control terminal for receiving a timing difference signal. The third switch includes a control terminal for receiving a reset signal. The capacitor is coupled between a charging terminal and a ground terminal. The signal synthesizer is for generating a timing signal according to a charging voltage and a reference voltage. The timing difference extractor is for generating a timing difference signal according to the timing signal and a deformed timing signal.

Abstract: A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.

Abstract: An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor.

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.