Patents Examined by Quinton A Brasfield
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Patent number: 11798979Abstract: An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.Type: GrantFiled: January 25, 2021Date of Patent: October 24, 2023Assignee: Texas Instruments IncorporatedInventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield, Joseph Andre Gallegos, Jay Sung Chun, Zhiyi Yu
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Patent number: 11739110Abstract: A compound having a first ligand of the following is described. Ring A represents a monocyclic aromatic group or a polycyclic aromatic group. Ring B represents a polycyclic aromatic group. Z is a carbon. Z and the right N are coordinated to a metal to form a five-membered chelate ring. R1 and R2 independently represent mono to a maximum possible number of substitutions, or no substitution.Type: GrantFiled: November 5, 2019Date of Patent: August 29, 2023Assignee: LUMINESCENCE TECHNOLOGY CORP.Inventors: Feng-Wen Yen, Tsun-Yuan Huang
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Patent number: 11735588Abstract: A semiconductor device includes a substrate having a first region and a second region. A device isolation layer is disposed in the substrate between the first region and the second region. The device isolation layer includes a buried dielectric layer in a trench that is recessed from a top surface of the substrate. A first liner layer is between the trench and the buried dielectric layer. A semiconductor layer is disposed on a top surface of the substrate of the first region. A first gate pattern is disposed on the semiconductor layer. A protrusion is disposed on a top surface of the device isolation layer.Type: GrantFiled: October 25, 2019Date of Patent: August 22, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Sic Yoon, Dongoh Kim
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Patent number: 11737296Abstract: The present disclosure provides an OLED display device, a display panel and a manufacturing method of the OLED display device, and belongs to the field of display technology. The OLED display device includes a light-emitting layer, a material of the light-emitting layer includes a host light-emitting material and a carrier balance material doped in the host light-emitting material; and the carrier balance material is used for balancing an electron mobility and a hole mobility of the light-emitting layer.Type: GrantFiled: December 23, 2019Date of Patent: August 22, 2023Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Xueqin Chen
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Patent number: 11721669Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.Type: GrantFiled: May 18, 2020Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Junyeong Heo, Jae-Eun Lee, Yeongkwon Ko, Donghoon Won
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Patent number: 11678574Abstract: Provided is a compound of Chemical Formula 1: HAr-L1-L2-Ar1??Chemical Formula 1 wherein: HAr is a group of the following Chemical Formula A-1 or A-2; L1 and L2 are the same as or different from each other, and each independently is a direct bond, a substituted or unsubstituted monocyclic or polycyclic arylene group, or a substituted or unsubstituted monocyclic or polycyclic heteroarylene group; and Ar1 is a substituted or unsubstituted monocyclic or polycyclic aryl group, or a substituted or unsubstituted monocyclic or polycyclic heteroaryl group; wherein: R1 to R3 are the same as or different from each other, and each independently is a substituted or unsubstituted linear or branched alkyl group; and is a site bonding to L1 of Chemical Formula 1, and an organic light emitting device comprising the same.Type: GrantFiled: March 22, 2019Date of Patent: June 13, 2023Assignee: LG CHEM, LTD.Inventors: Jungoh Huh, Sung Kil Hong, Dong Uk Heo, Miyeon Han, Jae Tak Lee, Junghoon Yang, Heekyung Yun
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Patent number: 11664369Abstract: A semiconductor device includes a semiconductor layer, a first conductor disposed on the semiconductor layer, a second conductor disposed on the semiconductor layer so as to be separated from the first conductor, a relay portion that is formed on the semiconductor layer so as to straddle the first conductor and the second conductor and that is made of a semiconductor having a first conductivity type region and a second conductivity type region, a first contact by which the first conductivity type region and the second conductivity type region are electrically connected to the first conductor, and a second contact that electrically connects the first conductivity type region of the relay portion and the second conductor together and that is insulated from the second conductivity type region.Type: GrantFiled: March 29, 2019Date of Patent: May 30, 2023Assignee: ROHM CO., LTD.Inventor: Yusuke Kubo
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Patent number: 11665961Abstract: The present specification relates to a hetero-cyclic compound represented by Chemical Formula 1, and an organic light emitting device comprising the same.Type: GrantFiled: October 18, 2018Date of Patent: May 30, 2023Assignee: LT MATERIALS CO., LTD.Inventors: Hyun-Ju La, Yu-Jin Heo, Won-Jang Jeong, Jin-Seok Choi, Dae-Hyuk Choi, Joo-Dong Lee
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Patent number: 11651976Abstract: Optical packages and methods of fabrication are described. In an embodiment, a controller chip is embedded along with optical components, including a photodetector (PD) and one or more emitters, in a single package.Type: GrantFiled: June 24, 2020Date of Patent: May 16, 2023Assignee: Apple Inc.Inventors: Kishore N. Renjan, Bilal Mohamed Ibrahim Kani, Kyusang Kim, Manoj Vadeentavida, Pierpaolo Lupo, Prashanth S. Holenarsipur, Praveesh Chandran, Vinodh Babu, Yuta Kuboyama
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Patent number: 11646143Abstract: Various devices are described (along with methods for making them), where the device has a tunnel barrier sandwiched between two magnetic layers (one of the magnetic layers functioning as a free layer and the other of the magnetic layers functioning as a reference layer). One magnetic layer underlies the tunnel barrier and the other magnetic layer overlies the tunnel barrier, thereby permitting spin-polarized current to pass across the magnetic layers and through the tunnel barrier. At least one of the magnetic layers includes a metal oxide sublayer (e.g., an MgO sublayer) sandwiched between magnetic material.Type: GrantFiled: May 21, 2019Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventor: Aakash Pushp
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Patent number: 11594597Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.Type: GrantFiled: October 25, 2019Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
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Patent number: 11563002Abstract: A semiconductor device includes a first fin that protrudes from a substrate and extends in a first direction, a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart, a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and a gate dielectric layer between the gate electrode and the second fin.Type: GrantFiled: May 21, 2019Date of Patent: January 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin Woo Kim, Choelhwyi Bae, Yang Gyeom Kim, Sung Eun Kim, Sang Woo Pae, Hyun Chui Sagong
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Patent number: 11545484Abstract: A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.Type: GrantFiled: January 15, 2021Date of Patent: January 3, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jui-Fa Lu, Chien-Nan Lin, Ching-Hua Yeh
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Patent number: 11538733Abstract: An electronic device includes a metal member and a connected member. A metal connecting layer is provided between a lower-side surface of the metal member and an upper-side surface of the connected member, to connect the metal member and the connected member to each other. The metal connecting layer includes at least one of metal films, each of which is made of gold or gold alloy. A thickness of the metal connecting layer in an opposing area between the metal member and the connected member is smaller than a flatness of each of the lower-side surface and the upper-side surface. A rust-preventing film is formed on a side wall of the metal member in such a way that the rust-preventing film extends from an outer periphery of the metal connecting layer to a position away from the outer periphery by a predetermined distance.Type: GrantFiled: July 2, 2020Date of Patent: December 27, 2022Assignee: DENSO CORPORATIONInventor: Toshihiro Miyake
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Patent number: 11532624Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.Type: GrantFiled: December 12, 2018Date of Patent: December 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Seok Jo, Jae-Hyun Lee, Jong-Han Lee, Hong-Bae Park, Dong-Soo Lee
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Patent number: 11527548Abstract: A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.Type: GrantFiled: December 11, 2018Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Haoyu Li, Everett A. McTeer, Christopher W. Petz, Yongjun J. Hu
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Patent number: 11527724Abstract: The present disclosure provides a hole transporting material, a method for preparing the same, and an electroluminescent device. The hole transporting material includes a compound of formula (I): A series of the hole transport materials with suitable HOMO/LUMO energy levels are synthesized by using bridged dihydrophenazine as a basis and different functional groups. Such materials can be applied to an organic electroluminescent device to improve mobility of a hole transport layer and thus improve luminous efficiency of the organic electroluminescent device.Type: GrantFiled: October 18, 2019Date of Patent: December 13, 2022Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Jiajia Luo
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Patent number: 11524970Abstract: Provided are a nitrogen-containing compound, an electronic element, and an electronic device, and relates to the technical field of organic materials. The nitrogen-containing compound is shown as formula I, and can reduce the working voltage of an electronic element, improve the efficiency of an OLED, and prolong the service life of an OLED.Type: GrantFiled: October 10, 2020Date of Patent: December 13, 2022Assignee: SHAANXI LIGHTE OPTOELECTRONICS MATERIAL CO., LTD.Inventors: Qiqi Nie, Chao Yu
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Patent number: 11515197Abstract: A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.Type: GrantFiled: July 11, 2019Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
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Patent number: 11502134Abstract: This disclosure relates to reduced power consumption OLED displays at reduced cost for reduced information content applications, such as wearable displays. Image quality for wearable displays can be different than for high information content smart phone displays and TVs, where the wearable display has an architecture that in includes, for example, an all phosphorescent device and/or material system that may be fabricated at reduced cost. The reduced power consumption can facilitate wireless and solar charging.Type: GrantFiled: March 3, 2020Date of Patent: November 15, 2022Assignee: Universal Display CorporationInventors: Michael Hack, Julia J. Brown, Michael Stuart Weaver, Woo-Young So