Abstract: A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 ?·cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.

Abstract: A method for dividing a package substrate into a plurality of device packages. The package substrate has a mount surface on the front side where a plurality of division lines are formed and a sealing layer formed on the back side, in which devices are sealed. The method includes a groove forming step of forming a groove along each division line on the mount surface of the package substrate so that the groove has a depth corresponding to a finished thickness of each device package, a burr removing step of removing burrs produced from electrodes in the groove forming step, and a grinding step of grinding the sealing layer of the package substrate so that a thickness of the package substrate is reduced to the finished thickness, after performing the burr removing step, thereby dividing the package substrate into the plural device packages.

Abstract: A substrate is mounted on a rotator provided in a reaction chamber, while a first process gas containing no source gas is supplied to an upper surface of the substrate from above the substrate and the substrate is rotated at 300 rpm or more, a temperature of a wall surface is changed, and after a temperature of the substrate is allowed to rise, the substrate is controlled to a predetermined film formation temperature and a second process gas containing a source gas is supplied to the upper surface of the substrate from above the substrate to grow an SiC film on the substrate.

Abstract: Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a sensor pixel array in a substrate, forming several transparent pillars over the substrate, and forming a light shielding layer over the substrate to cover the transparent pillars. The sensor pixel array has several sensor pixels, and each of the transparent pillars is correspondingly disposed on one of the sensor pixels of the sensor pixel array. The light shielding layer is a multi-layer structure. The method further includes performing a planarization process to expose the top surface of the transparent pillars.

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

Abstract: A display device includes: a first circuit board, wherein a first end of the first circuit board is attached to the panel pad area; and a second circuit board attached to a second end of the first circuit board, wherein the panel pad area includes a plurality of panel signal wirings, the second circuit board includes a plurality of circuit signal wirings, the first circuit board includes a first wiring layer including a plurality of first lead wirings coupled to the plurality of panel signal wirings, an insulating layer on the first wiring layer, and a second wiring layer on the insulating layer and electrically connected to the first wiring layer through the via hole, the plurality of first lead wirings includes a first sub-lead wiring, a second sub-lead wiring, and a first dummy lead wiring between the first sub-lead wiring and the second sub-lead wiring.

Abstract: The increasing power density and, therefore, current consumption of high performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate high frequency noise that results due to resonance between the package inductance and the onchip capacitance. In this paper, a novel circuit technique is proposed to suppress high frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the onchip power distribution network are suppressed by up to 60% as compared to MIM or deep trench decoupling capacitors of the same capacitance.

Abstract: A method of making a silicon on insulator structure comprises: providing a bonded structure, the bonded structure comprises the first substrate, the second substrate and the insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a first film; at a first temperature, performing a first etching to etch the first film to remove a first thickness of the first film; at a second temperature, performing a second etching to etch the first film to planarize the first film and remove a second thickness of the first film, the first temperature being lower than the second temperature, the first thickness being greater than the second thickness, and a sum of the first thickness and the second thickness being a total etching thickness of the first film.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.

Abstract: A method of manufacturing an oxide semiconductor, includes impregnating a substrate in a solution containing a metal precursor and hydroxyl ions, and forming a metal oxide on the substrate by applying a voltage to the solution. The solution includes a surfactant, and the direction of crystal growth of the metal oxide is controllable based on the surfactant.

Abstract: A display apparatus includes a first signal line and a second signal line that each extend on a substrate in a first direction and are spaced apart in a second direction that crosses the first direction; a plurality of first metal patterns spaced apart from each other in the first direction, wherein at least a portion of the first metal patterns overlaps the first signal line and is electrically connected to the first signal line; and a plurality of second metal patterns spaced apart from each other in the first direction, wherein at least a portion of the second metal patterns overlaps the second signal line and is electrically connected to the second signal line, wherein the plurality of first metal patterns and the plurality of second metal patterns are spaced apart in the first direction in a zigzag arrangement.

Abstract: A detachable structure comprises a carrier substrate and a silicon oxide layer positioned on the substrate at a first interface. The detachable structure is notable in that: the oxide layer has a thickness of less than 200 nm; light hydrogen and/or helium species are distributed deeply and over the entire area of the structure according to an implantation profile, a maximum concentration of which is located in the thickness of the oxide layer; the total dose of implanted light species, relative to the thickness of the oxide layer, exceeds, at least by a factor of five, the solubility limit of these light species in the oxide layer.

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

Abstract: Provided is a method for producing a thin film transistor that has a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode on a substrate. This method for producing a thin film transistor includes a step for forming the oxide semiconductor layer on the gate insulating layer by performing sputtering on a target with plasma. The step for forming the oxide semiconductor layer includes: a first film formation step in which only argon is supplied as a sputtering gas to perform sputtering; and a second film formation step in which a mixed gas of argon and oxygen is supplied as the sputtering gas to perform sputtering. A bias voltage applied to the target is a negative voltage of ?1 kV or higher.

Abstract: A method for manufacturing a semiconductor module for an image-sensing device is disclosed. The method may comprise forming a first molding component on a first surface of a printed circuit board (PCB); mounting at least a photosensitive member to a second surface of the PCB; and forming a second molding component on the second surface of the PCB. The PCB may comprise at least an electric component on the first surface of the PCB. The first molding component may encapsulate the at least one electric component with the PCB. The second molding component may secure the photosensitive member on the PCB.

Abstract: A spin coating method includes dispensing a coating material including a nonvolatile film material and a volatile solvent over a substrate, and spin coating the coating material over the substrate by spinning the substrate while applying ultrasound waves to the coating material to reduce a viscosity of the coating material during the spin coating.

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.