Patents Examined by R. Bahr
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Patent number: 11923844Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.Type: GrantFiled: April 28, 2022Date of Patent: March 5, 2024Assignee: Arm LimitedInventors: Seshagiri Rao Bogi, Vinay Chenani, Gurupadayya Shidaganti, Akshaykumar V Jabi
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Patent number: 11914439Abstract: A synchronous reset signal is generated from an asynchronous reset signal. The synchronous reset signal is output from the final-stage FF among L FFs connected in a cascade arrangement. A first error determination signal is output from the final-stage FF among M FFs connected in a cascade arrangement. Among N FFs connected in a cascade arrangement, the initial-stage FF receives the first error determination signal, and the final-stage FF outputs a second error determination signal. Based on the three outputs, the presence or absence of a fault in the circuit is determined. L, M, and N fulfil M?2, L?M+1, and M+N?L+1.Type: GrantFiled: March 17, 2020Date of Patent: February 27, 2024Assignee: Rohm Co., Ltd.Inventors: Hiromitsu Kimura, Yuji Kurotsuchi
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Patent number: 11900219Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.Type: GrantFiled: January 18, 2023Date of Patent: February 13, 2024Assignee: Rigetti & Co, LLCInventors: Colm Andrew Ryan, Eric Christopher Peterson, Marcus Palmer da Silva, Michael Justin Gerchick Scheer, Deanna Margo Abrams
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Patent number: 11894844Abstract: Rapid-data-transfer sensor arrays include a controller and a plurality of sensor integrated circuits (ICs) connected in series and configured to periodically take measurements and provide measurement data to the controller as serial data. A sensor IC includes a transducer, a shift register, a serial-data-in (SDI) pin, a serial-data-out (SDO) pin, a clock pin, and a bi-directional start/done (ST/DN) pin. The sensor IC includes a power regulation circuit configured to selectively supply power for a sleep mode and an active mode for recording data and an internal shift register. When finished with the measurement, the sensor IC is configured to provide measurement data to the shift register for transfer to the controller. The controller is configured to initiate serial transfer of data from each of the shift registers of the first plurality of sensor ICs to the controller. Examples include a 2D array.Type: GrantFiled: August 1, 2022Date of Patent: February 6, 2024Assignee: Allegro MicroSystems, LLCInventor: Matthew Hein
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Patent number: 11894217Abstract: A method of reducing reflected Radio Frequency (RF) power in substrate processing chambers may include accessing input parameters for a processing chamber that are derived from a recipe to perform a process on a substrate. The input parameters may be provided to a model that has been trained using previous input parameters and corresponding sensor measurements for the chamber. A predicted amount of reflected RF power may be received from the model and it may be determined whether the predicted reflected RF power is optimized. The input parameters may be repeatedly adjusted and processed by the model until input parameter values are found that optimize the reflected RF power. Optimized input parameters may then be provided to the chamber to process the substrate.Type: GrantFiled: February 21, 2023Date of Patent: February 6, 2024Assignee: Applied Materials, Inc.Inventors: Soonwook Jung, Kenneth D. Schatz
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Patent number: 11888479Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.Type: GrantFiled: October 1, 2021Date of Patent: January 30, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11888476Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.Type: GrantFiled: February 2, 2022Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daehyun Kwon, Hyejung Kwon, Hyeran Kim, Chisung Oh
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Patent number: 11881853Abstract: A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.Type: GrantFiled: June 16, 2022Date of Patent: January 23, 2024Assignee: International Business Machines CorporationInventors: Michael Berthold Kugel, Rolf Sautter, Amira Rozenfeld, Harry Barowski
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Patent number: 11876517Abstract: An electrical circuit includes a driver circuit, a receiver circuit, and a keeper circuit. The receiver circuit receives an input pulse from the driver circuit during a pre-charge phase. The receiver circuit generates an output pulse based on the input pulse during an evaluation phase. The keeper circuit maintains a charge of the output pulse until another evaluation phase, wherein the keeper circuit is adapted to the driver circuit by gating a first voltage supply of the driver circuit with a second voltage supply of the keeper circuit.Type: GrantFiled: February 11, 2022Date of Patent: January 16, 2024Assignee: International Business Machines CorporationInventors: Israel A. Wagner, Elazar (Eli) Kachir
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Patent number: 11867362Abstract: A wireless lighting control system is provided to create a lighting pattern by remotely controlling a plurality of lighting devices according to groups, thereby improving a lighting effect. The wireless lighting control system includes a first lighting device electrically connected with a first smart device to act as a master, and a plurality of second lighting devices electrically connected with a plurality of second smart devices to act as slaves, respectively. If a group for lighting control and control pattern information according to groups are selected from the first smart device, the first lighting device transmits the control pattern information according to the groups to the second lighting devices through a wireless communication scheme. At least one of lighting units of the second lighting devices and display units of the second smart devices is controlled based on the control pattern information according to the groups.Type: GrantFiled: February 13, 2023Date of Patent: January 9, 2024Assignee: FANLIGHT CO., LTD.Inventor: Ho Lim Song
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Patent number: 11863183Abstract: A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.Type: GrantFiled: October 15, 2021Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11863178Abstract: A method, system, and related component for detecting properness of a PG pin power-on timing sequence are provided. The method comprises: obtaining a pull-up level of a PG pin of a VR chip (S101); determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip (S102); obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value (S103); and outputting first prompt information when it is determined that an actual resistance of the pull-up resistor is lower than the first resistance or the second resistance (S104).Type: GrantFiled: December 30, 2019Date of Patent: January 2, 2024Assignee: Inspur Suzhou Intelligent Technology Co., Ltd.Inventor: Jian Wang
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Patent number: 11863184Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11848668Abstract: An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit to generate a delayed clock signal to enable the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state.Type: GrantFiled: September 7, 2022Date of Patent: December 19, 2023Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Milish Joseph, Michael Venditti
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Patent number: 11843373Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.Type: GrantFiled: October 29, 2021Date of Patent: December 12, 2023Assignee: SK hynix Inc.Inventors: Jin Ha Hwang, Soon Sung An, Junseo Jang, Jaehyeong Hong
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Patent number: 11836171Abstract: A system and method for processing queries including splitting a query into sub-queries, mapping the sub-queries to respective sets of filter properties, mapping the sets of filter properties to respective reconfiguration bitstreams, configuring a plurality of filters within a field programmable gate array (FPGA) according to respective ones of the respective reconfiguration bitstreams, wherein each filter is formed in a respective reconfigurable region of the FPGA.Type: GrantFiled: October 15, 2021Date of Patent: December 5, 2023Assignee: Google LLCInventor: Kiran Kalkunte Seshadri
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Patent number: 11830547Abstract: A reduced instruction set processor based on a memristor is provided. The memristor is a non-volatile device using a resistor to store “0” and “1” logic while implementing “implication logic” through applying a pair of voltages VCOND/VSET. Various data operations, logic operations, and arithmetic operations may be implemented based on the implication logic. The memristor is a computation and memory fusion device having great potential. A computer processor based on the memristor also becomes the research direction of the next-generation computer processor. The computer processor based on a memristor is designed according to the memory and computation fusion characteristic of the memristor. The processor is different from a traditional computer that must use a special memory and a calculator, and fuses computation and memory. Compared with a traditional computer, the speed, parallelism degree, and power consumption of the computer processor based on the memristor are greatly improved.Type: GrantFiled: November 29, 2018Date of Patent: November 28, 2023Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Qun Liu, Yewang Wang, Xiangshui Miao, Jian Li
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Patent number: 11831285Abstract: A driver circuit includes a first output terminal, a first switch, a second switch, a third switch and a power source. The first output terminal is arranged for outputting a data output. The first switch is selectively coupled between the first output terminal and a power supply node according to a data input. The second switch is selectively coupled between the first output terminal and a first reference node according to the data input. The third switch is selectively coupled between the first reference node and a reference voltage. The power source is configured to selectively provide one of a supply voltage signal and a supply current signal to the power supply node. When the power source is configured to provide the supply voltage signal, the third switch is switched on. When the power source is configured to provide the supply current signal, the third switch is switched off.Type: GrantFiled: October 22, 2020Date of Patent: November 28, 2023Assignee: M31 TECHNOLOGY CORPORATIONInventor: Ching-Hsiang Chang
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Patent number: 11824531Abstract: In a switching device and a system for converting a differential input signal into a ground-referenced output signal using a control signal, error states are detected, and detected error states lead to the deactivation of the ground-referenced output signal and are indicated on the control signal in addition.Type: GrantFiled: February 27, 2020Date of Patent: November 21, 2023Assignee: SEW-EURODRIVE GMBH & CO. KGInventors: Benjamin Norenburg, Christian Senft, Sebastian Richter, Hans Jürgen Kollar, Marco Mader
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Patent number: 11811402Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: November 7, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni