Abstract: A quantum circuit, including, a first S gates, a first Toffoli gate, a Controlled-SWAP gates, a Controlled-Toffli gates, a second Toffoli gate, and a second S gates.

Abstract: A method includes executing a calibration operation on a set of qubits, in a first iteration, to produce a set of parameters, a first subset of the set of parameters corresponding to a first qubit of the set of qubits, and a second subset of the set of parameters corresponding to a second qubit of the set of qubits. In an embodiment, the method includes selecting the first qubit, responsive to a parameter of the first subset meeting an acceptability criterion. In an embodiment, the method includes forming a quantum gate, responsive to a second parameter of the second subset failing to meet a second acceptability criterion, using the first qubit and a third qubit.

Abstract: A wireless lighting control system is provided to create a lighting pattern by remotely controlling a plurality of lighting devices according to groups, thereby improving a lighting effect. The wireless lighting control system includes a first lighting device electrically connected with a first smart device to act as a master, and a plurality of second lighting devices electrically connected with a plurality of second smart devices to act as slaves, respectively. If a group for lighting control and control pattern information according to groups are selected from the first smart device, the first lighting device transmits the control pattern information according to the groups to the second lighting devices through a wireless communication scheme. At least one of lighting units of the second lighting devices and display units of the second smart devices is controlled based on the control pattern information according to the groups.

Abstract: A control system is provides that includes a logic gate generating an output state signal, and first and second redundant controllers, wherein the first controller is configured to output a first state signal to a first input of the logic gate, and the second controller is configured to output a second state signal to a second input of the logic gate, and wherein the first controller is configured to receive an impedance isolated feedback signal corresponding to the second state signal from the second controller, and the second controller is configured to receive an impedance isolated feedback signal corresponding to the first state signal from the first controller, so that each controller can determine whether both inputs to the logic gate match one another.

Abstract: Systems, devices, computer-implemented methods, and/or computer program products that facilitate dynamic control of ZZ interactions for quantum computing devices. In one example, a quantum device can comprise a biasing component that is operatively coupled to first and second qubits via respective first and second drive lines. The biasing component can facilitate dynamic control of ZZ interactions between the first and second qubits using continuous wave (CW) tones applied via the respective first and second drive lines.

Abstract: A control device configured for use in a load control system to control an external electrical load may provide simple feedback regarding the operation of the control device. For example, the control device may comprise a base portion configured to be mounted to an electrical wallbox or over a mechanical switch, and a control unit connected to the base portion. The control unit may comprise a rotation portion rotatable with respect to the base portion, an actuation portion, and a light source. The control unit may be configured to control the light source to illuminate at least an illuminated portion of the actuation portion in response to actuations of the rotation portion and the actuation portion. In addition, the control unit may provide a limit indication on the illuminated portion by blinking the illuminated portion when the electrical load has reached a limit.

Abstract: Systems and methods are disclosed for controlling the operation of visual indicators, such as light emitting diodes (LEDs). A novel circuit may be employed to energize one indicator while de-energizing a second indicator, and vice versa. The novel circuit uses at least one switching component to perform a switching operation on the indicators.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: A planar flexible electrode arrangement for a dielectric barrier plasma discharge has a central region (107) and an edge region (108) and at least one planar electrode (102) to which a high-voltage potential can be applied and which is embedded in a planar dielectric (101) that forms an upper face (103) and a contact face (104), wherein the planar dielectric (101), at least in the edge region (108), has the shape of a spiral-shaped wound-up strip (109) and the at least one electrode (102) is formed by at least one electrical conductor (114) that extends in the longitudinal direction of the wound-up strip (109) and that opens into an end face of the strip (109), which conductor (114) is surrounded, with the sole exception of the end face of the strip (109), by the dielectric of the strip (109) and, in the region of the end face of the strip (109), is electrically insulated from the surroundings by a cover element (116).

Abstract: The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a programmable circuit includes: (1) a superconducting component arranged in a multi-dimensional array of alternating narrow and wide portions, the superconducting component having an input terminal at a first end and an output terminal at a second end opposite of the first end; and (2) control circuitry coupled to the narrow portions of the superconducting component, the control circuitry configured to transition the narrow portions between superconducting and non-superconducting states. In some implementations, the superconducting component and the control circuitry are formed on different layers of the programmable circuit.

Abstract: A hybrid computing system for solving a computational problem includes a digital processor, a quantum processor having qubits and coupling devices that together define a working graph of the quantum processor, and at least one nontransitory processor-readable medium communicatively coupleable to the digital processor which stores at least one of processor-executable instructions or data. The digital processor receives a computational problem, and programs the quantum processor with a first set of bias fields and a first set of coupling strengths. The quantum processor generates samples as potential solutions to an approximation of the problem. The digital processor updates the approximation by determining a second set of bias fields based at least in part on the first set of bias fields and a first set of mean fields that are based at least in part on the first set of samples and coupling strengths of one or more virtual coupling devices.

Abstract: An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.

Abstract: A method of reducing reflected Radio Frequency (RF) power in substrate processing chambers may include accessing input parameters for a processing chamber that are derived from a recipe to perform a process on a substrate. The input parameters may be provided to a model that has been trained using previous input parameters and corresponding sensor measurements for the chamber. A predicted amount of reflected RF power may be received from the model and it may be determined whether the predicted reflected RF power is optimized. The input parameters may be repeatedly adjusted and processed by the model until input parameter values are found that optimize the reflected RF power. Optimized input parameters may then be provided to the chamber to process the substrate.

Abstract: A quantum computer includes: a setting unit configured to set a parameter group of n layers based on each coefficient in a linear sum of unitary operators whose number is 2 to the n-th power, wherein the parameter group of k-th (2?k?n) layer is recursively set based on the parameter group of (k?1)-th layer; a quantum gate having n+m qubits including n auxiliary qubits and m target qubits, and configured to execute a predetermined calculation on an input value input to each qubit based the parameter group of n layers; and a specification unit configured to specify the linear sum of the unitary operators based on a calculation result of the quantum gate.

Abstract: A quantum write controller includes an in-phase path that includes a first digital to analog converter (DAC) configured to receive an in-phase signal at a first frequency, a first mixer configured to create a third in phase frequency, a first combiner configured to combine an output of the first mixer with an output of a third mixer, and a second mixer configured to mix an output of the first combiner with a fourth in phase frequency. There is a quadrature path that includes a second DAC configured to receive a quadrature phase signal at the first frequency, a third mixer configured to create a third quadrature frequency, a second combiner configured to combine the output of the third mixer with the output of the first mixer, and a fourth mixer configured to mix an output of the second combiner with a fourth quadrature frequency.

Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: A method of generating a randomized benchmarking protocol includes providing a randomly generated plurality of Hadamard gates; applying the Hadamard gates to a plurality of qubits; and generating randomly a plurality of Hadamard-free Clifford circuits. Each of the plurality of Hadamard-free Clifford circuits is generated by at least randomly generating a uniformly distributed phase (P) gate, and randomly generating a uniformly distributed linear Boolean invertible matrix of conditional NOT (CNOT) gate, and combining the P and CNOT gates to form each of the plurality of Hadamard-free Clifford circuits. The method also includes combining each of the plurality of Hadamard-free Clifford circuits with corresponding each of the plurality of Hadamard gates to form a sequence of alternating Hadamard-free Clifford-Hadamard pairs circuit to form the randomized benchmarking protocol; and measuring noise in a quantum mechanical processor using the randomized benchmarking protocol.

Abstract: A light fixture includes a communication input and output, a plurality of LED lights, an LED driver, first and second control modules, and a feedback circuit. The communication input is configured to receive a control signal. The communication output is configured to relay the control signal to a downstream light fixture. The LED driver is electrically coupled with the plurality of LED lights. The first control module is in signal communication with the communication input and output and the LED driver and is configured to transmit a driver signal to the LED driver that controls operation of the plurality of LED lights. The second control module is in signal communication with the first control module. The feedback circuit is in signal communication with the second control module and the LED driver. The LED driver transmits a feedback signal to the second control module via the feedback circuit.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.