Patents Examined by R. R. Kucia
  • Patent number: 4860166
    Abstract: A resistor terminating device is provided comprising: a substrate; and, a plurality of resistors supported on the substrate, such plurality of resistors having a plurality of electrically isolated connecting first ends arranged for alignment in overlaying relationship with a plurality of electrical conductive connecting leads adapted for electrical connection to such resistors.In a preferred embodiment of the invention, a printed circuit board is provided having disposed on a surface thereof a pattern of electrical conductors with ends thereof disposed in overlaying relationship with, and electrically connected to, a selected one, or ones, of the first electrode ends of the resistors.
    Type: Grant
    Filed: September 3, 1985
    Date of Patent: August 22, 1989
    Assignee: Raytheon Company
    Inventor: Robin P. Nicholls
  • Patent number: 4859808
    Abstract: An electrical interconnection lead pattern for connecting an integrated circuit to an electrical circuit comprises a plurality of electrical conductors and a plurality of non-continuous dielectric regions. Each conductor has a contact region wherein the conductor is subsequently electrically connected to a predetermined region on the integrated circuit. In addition, each of the contact regions are substantially parallel with respect to each and every other contact region. The dielectric regions comprise a material not amenable to soldering and are substantially parallel with respect to each and every other dielectric region so that the non-continuous regions between the dielectric regions are also substantially parallel. Lastly, the contact regions are substantially perpendicular with respect to each and every dielectric region, and disposed such that a portion of each of the contact regions contacts a portion of the non-continuous region between the dielectric regions and a portion of the dielectric region.
    Type: Grant
    Filed: June 28, 1988
    Date of Patent: August 22, 1989
    Assignee: Delco Electronics Corporation
    Inventors: Michael A. Jeter, Joseph S. Capurso
  • Patent number: 4855871
    Abstract: A thin film interconnect module utilizes a plurality of electroplated conductors disposed in one or more signal layers and surrounded by a dielectric having substantially the same thickness as the conductors to form a substantially planar layer. A metal/dielectric film is employed electrically to interconnect with various ones of the conductors during the electroplating process. After electroplating, selected ones of the electrical interconnections are broken by heating or irradiating selected ones of the interconnections. A dielectric-like film composed of microscopic non-contacting metal islands is used to link conductors that may subsequently need to be electrically connected, the electrical connection being achieved by melting the islands to form a continuous metal film. Interconnections between different planar layers may be achieved by the use of plated through holes. The process permits high density, high aspect ratio conductors to be fabricated on a multi-layer interconnect module.
    Type: Grant
    Filed: January 11, 1989
    Date of Patent: August 8, 1989
    Assignee: Optical Materials, Inc.
    Inventor: Peter L. Young
  • Patent number: 4855872
    Abstract: A leadless ceramic chip carrier (LCCC) is attached to an organic printed wiring board (PWB) via a Kapton.RTM. landing interface member. The LCCC terminals are soldered to conductors on the interface member whose conductors are also soldered to mating conductors on the PWB. The member is epoxied to the PWB to hold the member in place during vapor phase solder reflow of the different solder joints.
    Type: Grant
    Filed: August 13, 1987
    Date of Patent: August 8, 1989
    Assignee: General Electric Company
    Inventors: Jeffrey S. Wojnar, Joseph H. McCusker
  • Patent number: 4853491
    Abstract: A chip carrier and a process of assembling a chip carrier are disclosed. The carrier used for mounting a chip comprises a copper or copper base alloy component having a thin refractory oxide layer on a surface thereof. The surface and the oxide layer have an indentation formed therein for receiving the chip. A metallic circuit pattern for electrical connection to the chip is bonded to the oxide layer and insulated from the copper or copper base alloy by the refractory oxide layer. A seal is provided for enclosing the chip to the indentation. Another embodiment of the invention includes a circuit board structure comprising a circuit board device having a first coefficient of thermal expansion. A chip carrier is provided having a second coefficient thermal expansion of substantially the same value as the first coefficient of thermal expansion.
    Type: Grant
    Filed: September 27, 1985
    Date of Patent: August 1, 1989
    Assignee: Olin Corporation
    Inventor: Sheldon H. Butt
  • Patent number: 4851615
    Abstract: A composite comprises a first metal or alloy component having a thin refractory oxide layer on a first surface thereof. A second metal or alloy component has a second thin refractory oxide on the first surface thereof. Means are provided having a closely matched coefficient of thermal expansion to the first and second metal or alloy components for bonding the first and second thin refractory oxide layers and for electrically insulating the first component from the second component whereby thermal stress between the metal or alloy components and the bonding means is substantially eliminated.
    Type: Grant
    Filed: April 2, 1984
    Date of Patent: July 25, 1989
    Assignee: Olin Corporation
    Inventor: Sheldon H. Butt
  • Patent number: 4847446
    Abstract: A printed circuit board is described in which an electrically insulating laminate material has first and second sides. An electrically conducting first circuit pattern is embedded in the first side of the laminate material, and an electrically conducting second circuit pattern is embedded in the second side of the laminate material electrically insulated from the first circuit pattern by the laminate material. A solid interconnection member extends through the laminate material and electrically contacts both the first and second circuit patterns at selected locations thereof.The method for fabricating the board includes as a first step the fabrication of a first board panel having a raised electrically conducting first circuit pattern extending from a base layer of conductive material.
    Type: Grant
    Filed: June 2, 1988
    Date of Patent: July 11, 1989
    Assignee: Westinghouse Electric Corp.
    Inventors: David R. King, Mark S. Lee, Richard W. Decker
  • Patent number: 4847445
    Abstract: A thin-film metal conductor system using a zirconium adhesion layer is disclosed. The system is formed by first plating a layer of zirconium over a substrate material and any electrical components, such as resistors, which are fixed on the substrate. A conductive layer is then deposited over those portions of the zirconium layer which are to provide conductive pathways. The resulting unit is thermally treated in an oxidizing environment, such as air, to oxidize the exposed portions of the zirconium layer and thereby form regions of zirconium oxide. The zirconium oxide is nonconductive and protects underlying components from moisture and physical abrasion.
    Type: Grant
    Filed: February 1, 1985
    Date of Patent: July 11, 1989
    Assignee: Tektronix, Inc.
    Inventors: Earl R. Helderman, Robert E. Holmes, Robert R. Zimmerman
  • Patent number: 4847674
    Abstract: An interconnect (16', 18', 18"), whose interlevel contacts comprise refractory (10) to refractory or refractory to semiconductor substrate (13) interfaces, comprises patterned refractory core portions (10), consisting of tungsten or molybdenum, having top portions (10a) and opposed side portions (10b), provided with sidewall spacers (32a) of aluminum, gold or copper or alloys thereof and formed on surface (12a) of insulating layers (12). The sidewall spacers afford lateral low resistivity cladding of the refractory portions as well as suppression of the electromigration failure modes of voiding and whiskering, while leaving the top portion of the core portions available for refractory to refractory contacts and the bottom portion of the core portions available for refractory to refractory or refractory to silicon contacts.
    Type: Grant
    Filed: March 10, 1987
    Date of Patent: July 11, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jack Sliwa, Mohammad Farnaam, Pankaj Dixit, Lewis N. Shen
  • Patent number: 4845313
    Abstract: A metallic core printed circuit board having a number of lead terminals such as IC or LSI lead terminals provided on at least one edge of an electrically conductive substrate which forms a core by etching or other process. The respective terminals are electrically insulated from and secured to the core by an insulating binder, and then either conductor circuit patterns are directly formed on or a printed board wherein a printed circuit has been completed is bonded to the layer of the insulating binder. The metallic core printed circuit board makes it possible to increase a packaging density of required components, to allow easy connection to other circuit boards such as a mother board and the like, and to reduce a volume of the circuit.
    Type: Grant
    Filed: March 19, 1987
    Date of Patent: July 4, 1989
    Assignee: Tokyo Communication Equipment Co., Ltd.
    Inventors: Satoru Endoh, Ohnishi Katsuga
  • Patent number: 4845592
    Abstract: A bussing system 10 for panels 11, such as a printed circuit board employs bus means comprised of at least one ribbon 16 of flexible, relatively thin, substantially flat, conductive material, such as copper. Ribbon 16 is bent as desired to be received within a plurality of taps, including at least one vertical tap 13, mounted on the panel at selected respective locations. The taps may also include at least one horizontal tap 14, in which case ribbon 16 is twisted to right angles thereto to be received in the horizontal tap. One or more standoffs 15 may be employed to maintain mechanical rigidity and to maintain ribbon 16 in a vertical orientation off of panel 11. The amount of copper (or other material) employed is held to a minimum to meet the circular mil area (or "CMA") requirements. Design flexibility is assured for accommodating a variety of configurations, thereby effecting a considerable savings in development, tooling and production costs.
    Type: Grant
    Filed: August 31, 1987
    Date of Patent: July 4, 1989
    Assignee: AMP Incorporated
    Inventors: John L. Himes, Jr., James H. Wise
  • Patent number: 4841100
    Abstract: A retainer post for tightly engaging a printed circuit board employing surface mounted technology. The retainer post has a hollow neck portion for insertion in a hole in a printed circuit board, an adjoining shoulder section for engaging the surface of the printed circuit board and, preferably, a retaining means for retaining said post in the printed circuit board. The retaining means preferably is formed of a circumferential, radially projecting barb containing longitudinal notches so that it may be inwardly compressed as the retaining post is inserted in a hole in a printed circuit board. The neck section contains a plurality of longitudinal spaced (i) grooves on its outer surface forming opposing frangible webs or (ii) cuts through said neck section. The neck section contains a cavity in which is disposed a material that expands upon heating.
    Type: Grant
    Filed: September 2, 1987
    Date of Patent: June 20, 1989
    Assignee: Minnesota Mining and Manufacturing Company
    Inventor: Martin C. Ignasiak
  • Patent number: 4839775
    Abstract: The invention relates to a thick-film circuit arrangement having an electronic circuit which is constructed on a surface (17) of a ceramic substrate plate (3) and which consists of conductor paths (5), resistors, capacitors and components, in particular integrated switching circuits without a housing, formed according to thick-film technique. This structure has between the electrically conductive structures (5) a sintered, nonconductive paste substantially filling the intermediate spaces between them and both the structures and the interposed pastes are covered by a sintered insulating paste. For concealing the thick-film circuit arrangement from unauthorized access, the following covering construction is carried out:1.
    Type: Grant
    Filed: June 14, 1988
    Date of Patent: June 13, 1989
    Assignee: U.S. Philips Corporation
    Inventors: Wolfgang E. Schnitker, Michael P. J. Nover, Kay Appel
  • Patent number: 4837407
    Abstract: A plastic electrically insulating substrate, having high thermal conductivity, for wiring circuit boards including a substrate having a front surface for mounting an electrical device back surface.The substrate is made of a laminate of a plurality of oriented sheets of one or more semicrystalline polymers having a uniform oriented direction of the sheets, and wherein the oriented direction of the sheets is arranged in the direction of the substrate thickness.
    Type: Grant
    Filed: March 30, 1987
    Date of Patent: June 6, 1989
    Assignee: Aisin Seiki Company, Ltd.
    Inventor: Shinji Nezu
  • Patent number: 4837408
    Abstract: A multilayered wiring board comprising a plurality of green sheets of crystallizable glass which have a conductive pattern printed thereon. The green sheets are laminated together and sintered as a unit. The conductive composition used for the conductive pattern mainly comprises Cu or CuO with lesser amounts of MnO.sub.2. According to two embodiments the conductive composition additionally contains (1) Pd and/or Pt or (2) Ag.sub.2 O and TiO.sub.2 or TiH.sub.2. Thereby volume contraction due CuO reduction cancels out volume expansion due to Cu oxidation in the subsequent degreasing.
    Type: Grant
    Filed: May 20, 1988
    Date of Patent: June 6, 1989
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kazuo Kondo, Asao Morikawa, Hiroshi Iwata
  • Patent number: 4833570
    Abstract: An electronic circuit assembly includes a printed cirucit base plate, an electronic circuit element, a spacer and a coating resin. The electronic circuit element includes an IC housing and a plurality of lead pins. The plurality of lead pins are electrically connected and secured to the printed circuit base plate such that the IC housing is spaced apart from the printed circuit base plate. The spacer is located between the printed circuit base plate and the IC housing. The coating resin coats the printed circuit base plate, a portion of the spacer and a portion of the lead pins of the electronic circuit element.
    Type: Grant
    Filed: November 3, 1987
    Date of Patent: May 23, 1989
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tatsuo Teratani
  • Patent number: 4831497
    Abstract: A circuit assembly including a plurality of integrated circuit chips wherein electrical interconnections between chips at a relatively large distance from each other are accomplished by a conductor bus comprising a first section including conductors running adjacent and parallel to each other for a distance substantially equal to an integral number of half wavelengths of the base frequency of signals of the circuit and second sections including conductors which sharply diverge toward associated integrated circuit chips for electrical connection therewith.
    Type: Grant
    Filed: September 11, 1986
    Date of Patent: May 16, 1989
    Assignee: General Electric Company
    Inventors: Harold F. Webster, John P. Quine
  • Patent number: 4829405
    Abstract: The disclosure describes a new and improved Tape Automated Bonding package which admits of certain advantages that are not available with the packages as used in the past, and it overcomes some limitations with the previous packages which permits a significant step forward in realizing these advantages.Briefly, the disclosure describes a division of the dielectric support used to package integrated circuit chips in order to separate the power conductors and the signal conductors into different parts of the support. The conductors formed on at least one of these parts, preferably the part used to connect input/output signals to and from a chip, are arranged in radially extending rows to achieve more than twice the number of such connections.
    Type: Grant
    Filed: March 14, 1988
    Date of Patent: May 9, 1989
    Assignee: International Business Machines Corporation
    Inventor: Keith A. Snyder
  • Patent number: 4827083
    Abstract: A wiring substrate which may be sintered with a minimum of cracking of the via-fills has a wiring substrate with wiring layers made of paste containing palladium powder and silver powder composed of spherical silver particles and flake-like silver particles, insulating layers made of a ceramic material and through-hole wirings formed by the paste within the insulating layers to provide electrical connection between the wiring layers.
    Type: Grant
    Filed: April 7, 1988
    Date of Patent: May 2, 1989
    Assignee: NEC Corporation
    Inventors: Jun Inasaka, Shin-Ichi Hasegawa
  • Patent number: 4827328
    Abstract: A compact and dense hybrid integrated circuit device which can be encapsulated by transfer molding can be manufactured by forming through holes in a ceramic or glass substrate, which through holes have a diameter of less than 0.2 mm, preferably less than 0.1 mm, a thin film circuit element being formed on one surface of the substrate, and a thin or thick film circuit element being formed on the other surface of the substrate. A fine through hole as mentioned above can be formed by laser drilling, etc., and plating.
    Type: Grant
    Filed: March 17, 1987
    Date of Patent: May 2, 1989
    Assignee: Fujitsu Limited
    Inventors: Takashi Ozawa, Ichiro Munakata, Hiroaki Takagi, Ryoichi Kozaki