Abstract: A method of additive encoding of data words includes receiving a plurality of data words, and searching a trellis representation of additive code words to identify a path in the trellis representing a sequence of patterns to be used to encode the data words. The trellis representation is of all possible combinations of matching patterns in a sequence of additive code words. The trellis representation of the additive code words is searched to identify a sequence of flags representing the sequence of patterns to be used to encode the data words.

Abstract: A system and method to transmit and receive forward error corrected data in a diversity communications system is provided. Using diversity techniques, multiple copies of the transmitted data are received with varying degrees of corruption due to channel impairments. In addition to the multiple copies of forward error corrected data, an additional data set of implicit parity bits is used in the data decoding process, wherein the reliability of these parity bits is assumed to be very high. The implicit parity bits are not transmitted or received by the system, but are introduced in the receivers' decoding process. These implicit parity bits add an extra highly reliable dimension of forward error correction codes. Therefore the present system and methods provide an improved data decoding process with high coding gain and channel efficiency, while minimizing system resources.

Abstract: An improved method and apparatus for performing single-cycle operations (such as for example Maximum a Posteriori, i.e. MAP decode) in digital processors is disclosed. In one exemplary configuration, a processor is fitted with a specialized instruction and extension Arithmetic Logic Unit (ALU) to efficiently perform the forward and reverse transition trellis metric updates as well as the Log Likelihood ratio calculation in order to accelerate the decoding of Turbo-encoded data sequences. The processor executes software comprising the single operand instruction to perform Turbo decoding with the efficiency comparable to a dedicated hardware implementation. The programmable apparatus can be readily reprogrammed to accommodate evolving standards.

Abstract: Disclosed are a digital display apparatus and method. The digital display apparatus includes a signal intensity detect unit, a tuner unit, a control unit, and a digital signal process unit. The signal intensity detect unit divides a digital input signal received through an antenna into a strong signal and a weak signal based on a predetermined level. The tuner unit amplifies the weak signal, bypasses the strong signal, demodulates each signal and outputs a digital stream. The control unit receives the digital stream and determines whether an error is generated, and if the error is generated, outputs a conversion signal to reverse a working state of the tuner unit. The digital signal process unit receives the digital stream and converts it to a signal type that can be outputted if the error is not generated. Accordingly, breaking or freezing of a video on the digital display apparatus can be compensated.

Abstract: A communication circuit in a network interface adapter for performing a checksum. One embodiment of the invention includes a network interface adapter having a network interface operable to receive a data packet having a header and a processor coupled to the network interface and operable to perform a checksum operation on each received data packet and operable to change the received data packet in response to the checksum operation. More specifically, the header in each received data packet is changed to a specific pattern of bits to indicate, in an easily recognizable manner, whether the received data packet has passed or failed the checksum.

Abstract: A data buffer receives and temporarily stores data including a product code enabling error correction in first and second directions. An exclusive-OR operation circuit uses an error amount detected by error correction in the first direction and data stored in a storage element to calculate a first error check result. A PI direction error-checking circuit according to the first error check result performs error check after error correction in the first direction. A PO direction partial error-checking circuit and a PO direction aggregate error-checking circuit use an error amount detected in error correction in the second direction and calculate a second error check result. The first and second error check results are used to generate a final error check result by an exclusive-OR operation circuit.

Abstract: An apparatus and method for generating an encoding matrix for a low density parity check (LDPC) code having a dual-diagonal matrix as a parity check matrix are disclosed. The apparatus and method construct an information sub-matrix of the encoding matrix with a predetermined number of square matrixes according to a predetermined code rate such that each of the square matrixes has columns and rows with a weight of 1 and has a different offset value, combine the square matrixes with the dual-diagonal matrix, and perform inter-row permutation on the information sub-matrix.

Abstract: Data is read from a recording medium and the reproduced data is deinterleaved and stored to a first memory while input/output to/from the first memory is arbitrated. It is determined whether a predetermined number of data units is stored to the first memory. Based on the result data, it is determined whether transfer of the data stored in first memory to a second memory is permitted. If data transfer is permitted, the reproduced data is transferred from the first memory to the second memory, during which time input/output to/from the second memory is arbitrated. The reproduced data stored to the second memory is then error corrected, and user data contained in the error corrected reproduction data is externally output from the second memory.

Abstract: A method and apparatus for communicating data is provided. The data is encoded in accordance with a run length limited (RLL) code. A seed is appended to the RLL encoded data. The seed can be used to alter the error correction code (ECC) parity to meet an RLL constraint.

Abstract: A deterministic structure for controlled distribution of weight-2 columns is proposed for a parity-check matrix H that reduces the occurrence of undetected frame errors and significantly enhances the code performance in comparison to a randomly-constructed parity-check matrix. H comprises a non-deterministic section H1 and a deterministic section H2, and wherein H2 comprises a first part comprising a column h having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, 0 elsewhere.

Abstract: A transport format determination apparatus and method determines, for each transport channel, transport formats to be used for supplying data every data-arrival-interval. A plurality of transport channels different in data-arrival-interval are free to be multiplexed with each other. A fault of data on the plurality of transport channels is detected. At least one first data-arrival-interval of at least one first transport channel is determined, based on a result of detecting fault of data on a second transport channel having a second data-arrival-interval shorter than the at least one first data-arrival-interval. A candidate of transport format combination indicators to be used for decoding post-received data and for isolating transfer blocks is restricted.

Abstract: A circuit for generating tracking error signal using differential phase detection, comprising a quadrant photodetector for receiving optical signal and inducting splitting signal A, splitting signal B, splitting signal C and splitting signal D, two adders for generating group signal (A+C) and group signal (B+D). A plurality of equalizers for receiving, equalizing and amplifying splitting signal A, splitting signal B, splitting signal C, splitting signal D, group signal (A+C) and group signal (B+D). A plurality of phase detectors for receiving the output of equalizers and comparing phase difference of splitting signal A and group signal (A+C), group signal (A+C) and splitting signal B, splitting signal C and group signal (B+D), and group signal (B+D) and splitting signal D, and outputting a plurality of adjustment signals respectively. A circuit for eliminating the phase difference by adding and subtracting some adjustment signals with same phase difference.

Abstract: An error correction method is provided as follows: handling a 2-event error generated very frequently as an object of correction; sequentially finding CRC data for a generated event of an error handled as the defined object of correction at any arbitrary bit position of reproduced data by implementation of a cyclic-replacement process; carrying out an exclusive-addition process of the CRC data to CRC data of the reproduced data in order to virtually carry out a tentative-correction process on a 1-event error at a first bit position; further finding CRC data generated after the tentative-correction process in order to detect a 1-event error at a second bit position; and correcting the 1-event error completing the tentative-correction process at the first position and the 1-event error at the second bit position.

Abstract: The invention relates to an error correcting decoder apparatus (100) and method. The decoder apparatus (100) comprises a likelihood estimator (101) which generates a sequence of bit value likelihood estimates, such as log likelihood ratios, for multi bit symbols of a data sequence. The decoder apparatus (100) further comprises a decoder element (103), such as a Maximum A Priori (MAP) or appropriate Soft Output Viterbi decoder. The decoder element (103) generates a decoded data sequence in response to the bit value likelihood estimates. The decoder apparatus (100) also comprises a weighted processor (105) which generates a weighted compensation data sequence from the decoded data sequence. The weighted compensation data is used to modify the sequence of bit value likelihood estimates. The decoding is subsequently repeated using the improved bit value likelihood estimates whereby improved decoding performance is achieved.

Abstract: Device and method for inserting error correcting codes and for reconstructing data streams, and corresponding products The present invention relates to a device (1) for inserting error correcting codes into data streams (11) intended to be sent in packets in a network (8), a device (9) for reconstructing data streams (13), and corresponding methods and products. The insertion device comprises a unit (3) for identifying resynchronization indicators dispersed in the data streams and a unit (4) for determining successive segments in these streams, the segments forming partitions of the data lying between two consecutive resynchronization indicators. It also comprises a unit (6) for allocating a set of error correcting codes to each of these segments, these sets of codes having decreasing sizes between any two of the consecutive resynchronization indicators. Preferably, the device also comprises a data interleaving unit (7).

Abstract: A method and apparatus for communicating a message from a transmitting station to a remote receiving station by adaptively selecting a retransmission protocol from two or more retransmission protocols based on at least one changing transmission variable is described herein. The transmitting station transmits a first version of the message in a first transmission. When the previous transmission was unsuccessful, a controller adaptively selects either the first version of the message or a second version of the message in accordance with the selected protocol.

Abstract: An apparatus has an integrated circuit that includes a seed register, a linear feedback shift register to load a test vector into a number of scan chains, and a signature register to receive a test response from the scan chains. The seed register, the linear feedback shift register, and the signature register each have the same register length. The linear feedback shift register and the signature register have the same shift frequency that is greater than a frequency at which a seed vector is loaded into the seed register. The linear feedback shift register is adapted to be selectively provided with bits to control a degree to which its vector is dependent on previous vectors. The scan chains may be configured as a single group providing a test response to a single input signature register or a set of groups providing a test response to a multiple input signature register.

Abstract: An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB. When the received and stored MSB's match, the full L bits are compared. When the received word is larger than the stored word, the largest mis-matching bit in the LSB is found, and bits above this are copied from the received LSB to the stored register, while lower bits are generated to produce the lowest value. Repeating the process converges the result.

Abstract: A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit (38) is disclosed. The LDPC code is arranged as a parity check matrix (H) whose rows and columns represent check sums and input nodes, respectively. The parity check matrix is grouped into subsets of check sum rows, in which the column weight is a maximum of one. The decoder circuitry includes a parity check value estimate memory (52). Adders (54) generate extrinsic estimates, from immediately updated input node probability estimates, and the extrinsic estimates are applied to parity check update circuitry (56) for generating new parity check sum value estimates. These parity check sum value estimates are stored back into the memory (52), and after addition with the extrinsic estimates, are stored in a column sum memory (66) of a corresponding bit update circuit (60) as updated probability values for the input nodes.

Abstract: A method and a configuration produce a fault signal that is suitable for identifying transmission faults when using differential signaling. A first mid-level signal whose potential is in the area of the mid-point between the signal level on a first signal line and a signal level on a second signal line, when a logic “1” is transmitted is compared with a second mid-level signal formed when a logic “0” is transmitted. The fault signal is produced if the discrepancy between the two mid-level signals is greater than a predetermined threshold value.