Abstract: The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplier is selected to generate a finite basic field of a predetermined number of elements. The array has M rows and N columns, such that M is greater than or equal to three and N is greater than or equal to three. Row 1 through row M?2 of the array each have n–p data storage devices and p parity storage devices. Row M?1 of the array has n?(p+1) data storage devices and (p+1) parity storage devices. Lastly, row M of the array has N parity storage devices.

Abstract: An error detecting method and apparatus may be provided for a moving image transmitting system. An error detection code may be generated for each data block of a frame. The generated error detection code may be inserted into a byte alignment code of the data block. The frame may then be transmitted from a transmitting side to a receiving side. A byte alignment code may be extracted from each data block after the frame is received at the receiving side. Errors may be detected based on the extracted code. The method may enable a moving image encoder to be stably operated and allow improvement of the picture quality. Also, the method may allow the byte alignment code, which has been regarded as meaningless information, to be associated with a channel code so as to enhance error detection efficiency.

Abstract: A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.

Abstract: A circuit for evaluating characteristics of duration and/or shape of an electric pulse induced in an element of an integrated circuit comprising an assembly of elements, each element being likely to receive an occasional external disturbance generating an electric pulse in the element, and a measurement circuit connected to the elements to determine said characteristics of an electric pulse generated in one of the elements.

Abstract: A CD-ROM decoder for processing digital data while buffering the digital data in a buffer RAM. The CD-ROM decoder includes a host interface for storing the digital data in the buffer RAM. An EDC processing circuit generates an error detection code using the digital data read from the buffer RAM in a block unit. An ECC processing circuit generates an error correction code with the digital data and the error detection code. An internal RAM stores the digital data and adds the error detection code and the error correction code to the digital data when storing the digital data. A digital signal processor outputs the digital data, the error detection code, and the error correction code that are stored in the internal RAM in a block unit.

Abstract: Methods and apparatus to optimize delivery of multicast content using probabilistic feedback. A method is provided for transmitting data from a server to a plurality of receiving terminals. The method includes transmitting the data from the server to the plurality of receiving terminals, and generating a random response value at each receiving terminal. The method also includes comparing the response value to an acknowledgement value at each receiving terminal, and transmitting an acknowledgment signal to the server from selected receiving terminals. The selected receiving terminals are a portion of the plurality of receiving terminals where the response value has a selected relationship to the acknowledgement value.

Abstract: The present invention is to reduce the maximum magnetization reversal interval of a trellis code. A trellis diagram for the trellis code takes into consideration a constraint condition on the DSV of a code and an inter-symbol-interference for three bits. The minimum squared Euclidean distance is 4. When a non-interleaving encoder and a non-de-interleaving code detector are constructed using the trellis diagram, the maximum magnetization reversal interval of a trellis code to be used is reduced to half of that in a known case while having the error rate and circuit size approximately equal to those in the known case. The trellis diagram has a basic repeating unit for two bits. In the actual apparatus, the trellis diagram is repeatedly used. The present invention is applicable to a read/write apparatus.

Abstract: In some embodiments, a first comparator compares a first error rate and a first threshold value and a second comparator compares a second error rate and a second threshold value. Other embodiments are described and claimed.

Abstract: A transmit process that limits the time during which a reduced network bandwidth exists between two powerline nodes because a receiving node fails to respond to frame transmission attempts by a transmitting node is described. The transmit process restricts the number of retries that occur in a lower date rate transmission mode and, for a predetermined time period to follow, drops all subsequent frames destined for the non-responding node.

Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

Abstract: Methods and systems for streaming data in a network. Whether the network is experiencing high packet loss may be determined by a rate control module. If high packet loss is experienced, data is encoded into multiple streams by a coder using temporal domain partitioning. If high packet loss is not experienced, then data may is encoded by using frequency domain partitioning. Unequal error protection is applied to each of the streams so more important bit planes in a bit of a stream are provided with more error protection than less important bit planes. The streams are transmitted along, respectively, independent paths to a decoder. The streams are decoded, and errors in the decoded streams are corrected by using information from one or more of the other decoded streams. The decoded corrected streams are reconstructed into the data.

Abstract: An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.

Abstract: A programmable time event and waveform generator for the application of precise timing patterns to a logic circuit and the capture of response data from the logic circuit. The time event and waveform generator comprises a programmable delay element that is programmed with values stored in pattern memory. For scan based testing, the time event and waveform generator is programmed between test pattern scan sequences by serial loading from the test pattern memory. The generator may be used to generate precise signal transitions to input pins of a circuit under test, and to capture at precise times the signal states from the output pins of a circuit under test. The data for programming the delay element is accessed from test pattern memory.

Abstract: A fault or an exception is injected into a target thread. Instructions are processed and a target thread is recognized. As a result, an asynchronous procedure call is queued. The asynchronous procedure call is run on the target thread and the context of the target thread is modified. The target thread is executed in the modified context and an exception is raised in the target thread as a result of the modified context. The exception is handled and processing of the instruction continues.

Abstract: The present invention discloses an apparatus used to generate a branch metric for a Viterbi decoder. The apparatus includes a linear feedback shift register and a convolutional encoder. The linear feedback shift register performs a calculation based on a specific primitive characteristic polynomial and creates a binary number sequence after the calculation. The convolutional encoder generates the branch metric by encoding the binary number sequence. Besides, the apparatus is further capable of selecting one of the several built-in primitive characteristic polynomials by inputting a selection signal in order to conform to the request of the different systems.

Abstract: Two types of codings are integrated, instead of performing each coding independently. The two codings may be integrated by interleaving one or more acts of one coding method (e.g. data coding) between two or more acts of the other coding method (e.g. line coding). In some embodiments, partitioning of a block of data (e.g. a byte) for line coding (e.g. DC balance coding) is done prior to data coding (e.g. error correction coding). In such embodiments, the remaining acts of line coding may be performed after the data coding is completed. In one particular embodiment, an 8 bit byte is not directly used in error correction coding and instead, the 8 bit byte is initially partitioned into two sub-blocks (of 3 bits and 5 bits) as required by 8B/10B encoding (which is an example of line coding). After partitioning, the 8B/10B encoding is not continued, and instead Reed Solomon coding (which is an example of data coding) is then performed (to completion) on the individual sub-blocks (of 3 bits and 5 bits).

Abstract: The invention discloses a data validation, mirroring and error/erasure correction method for the dispersal and protection of one and two-dimensional data at the micro level for computer, communication and storage systems. Each of 256 possible 8-bit data bytes are mirrored with a unique 8-bit ECC byte. The ECC enables 8-bit burst and 4-bit random error detection plus 2-bit random error correction for each encoded data byte. With the data byte and ECC byte configured into a 4 bit×4 bit codeword array and dispersed in either row, column or both dimensions the method can perform dual 4-bit row and column erasure recovery. It is shown that for each codeword there are 12 possible combinations of row and column elements called couplets capable of mirroring the data byte. These byte level micro-mirrors outperform conventional mirroring in that each byte and its ECC mirror can self-detect and self-correct random errors and can recover all dual erasure combinations over four elements.

Abstract: A forward error correction system comprises a forward error correction (FEC) manager and a transmitter. The FEC manager is configured to receive a data stream and to define a plurality of FEC code words based on the data stream. Each of the FEC code words comprises a data portion and a checksum portion that may be used to recover at least one character of the data portion. The FEC manager is configured to interleave characters of the FEC code words such that the FEC code words are transmitted, by the transmitter, to a remote receiver in an interleaved fashion. The FEC manager is configured to provide characters from each of the FEC code words to the transmitter before a plurality of characters to be assigned to each of the FEC code words has been received by the FEC manager.

Abstract: A method and apparatus for performing quickly and efficiently generating the error correction polynomial. In accordance with the present invention, multiple coefficients of the syndrome vector are processed in parallel by a Berlekamp algorithm logic block of the present invention. The Berlekamp algorithm's iterations can be performed in less than 60 clock cycles for a large order error correction polynomial, thereby enabling the polynomial to be generated very rapidly. In order to perform the Berlekamp algorithm at such a high rate of speed, Galois field multiplier logic is utilized in performing the algorithm.

Abstract: A communication device capable of correcting a burst error exceeding a correcting capability of an error correcting code by only transmitting one packet. With respect to data to be transmitted, a frame generating section 22 generates a frame for which an error detecting process, etc., is performed. A frame dividing section 23 divides the generated frame, by a predetermined number, into a plurality of divided frames. A transmission control section 24 generates a packet in which the plurality of divided frame are copied predetermined times. A transmitting section 25 sends the packet to a receiver. A receiving section 35 receives the packet transmitted from a transmitter. A reception control section 34 divides the received packet by the predetermined number. A frame reconstructing section 33 reconstructs the frame by assembling the divided frames in predetermined order. A frame processing section 32 performs an error correcting process, etc., for the reconstructed frame.